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1. 发明申请

US20050248382A1 Resistor compensation apparatus 失效
标题翻译：电阻补偿装置
公开(公告)号：US20050248382A1
公开(公告)日：2005-11-10
申请号：US10840524
申请日：2004-05-06
申请人： David Chung , Afshin Momtaz , Mario Caresosa
发明人： David Chung , Afshin Momtaz , Mario Caresosa
IPC分类号： G06G7/12
CPC分类号： H03F3/4508 , H03F2200/456 , H03F2200/465 , H03F2203/45292 , H03F2203/45541
摘要： A compensation apparatus maintains an effective resistance of one or more resistors in a circuit by associating an adjustable resistor circuit to each resistor. The compensation apparatus compares the resistance of a resistor in the circuit with the resistance of a reference resistor. When the resistance of the resistor in the circuit falls outside of a desired range, the compensation apparatus adjusts the resistance of the adjustable resistor to adjust the effective resistance of the resistor and adjustable resistor combination.
摘要翻译：补偿装置通过将可调电阻器电路与每个电阻器相关联来保持电路中的一个或多个电阻器的有效电阻。补偿装置将电路中的电阻器的电阻与参考电阻器的电阻进行比较。当电路中的电阻电阻超出所需范围时，补偿装置调整可调电阻的电阻，调整电阻和可调电阻组合的有效电阻。

2. 发明申请

US20100046601A1 HIGH SPEED RECEIVE EQUALIZER ARCHITECTURE 有权
标题翻译：高速接收均衡器结构
公开(公告)号：US20100046601A1
公开(公告)日：2010-02-25
申请号：US12606751
申请日：2009-10-27
申请人： Afshin Momtaz , Mario Caresosa , David Chung , Davide Tonietto , Guangming Yin , Bruce Currivan , Thomas Kolze , Ichiro Fujimori
发明人： Afshin Momtaz , Mario Caresosa , David Chung , Davide Tonietto , Guangming Yin , Bruce Currivan , Thomas Kolze , Ichiro Fujimori
IPC分类号： H03K5/159
CPC分类号： H04L7/033 , H03G3/3084 , H03L7/091 , H04L25/03057 , H04L2025/03375 , H04L2025/03617
摘要： Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.
摘要翻译：公开了各种示例性实施例。根据示例实施例，设备可以包括连续时间滤波器，判决反馈均衡器，时钟和数据恢复电路以及适配电路。适配电路可以被配置为通过基于均衡数据信号的均方误差调整延迟调整信号来根据至少一个抖动算法来适应均衡。

3. 发明授权

US07623600B2 High speed receive equalizer architecture 有权
标题翻译：高速接收均衡器架构
公开(公告)号：US07623600B2
公开(公告)日：2009-11-24
申请号：US10880959
申请日：2004-06-30
申请人： Afshin Momtaz , Mario Caresosa , David Chung , Davide Tonietto , Guangming Yin , Bruce Currivan , Thomas Kolze , Ichiro Fujimori
发明人： Afshin Momtaz , Mario Caresosa , David Chung , Davide Tonietto , Guangming Yin , Bruce Currivan , Thomas Kolze , Ichiro Fujimori
IPC分类号： H04L27/08
CPC分类号： H04L7/033 , H03G3/3084 , H03L7/091 , H04L25/03057 , H04L2025/03375 , H04L2025/03617
摘要： Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.
摘要翻译：在高速通信接收机中提供均衡，其包括各种方面的自动增益控制输入级，判决反馈均衡器，时钟和数据恢复电路以及均衡控制电路。自动增益控制级可以包括具有可调节带宽的连续时间滤波器。阈值调整信号可以应用于自动增益控制级的输出。均衡控制电路可以在数字域中实现并且以比数据路径更低的时钟速度工作。

4. 发明授权

US07324548B2 Transceiver system and method supporting variable rates and multiple protocols 有权
标题翻译：收发器系统和支持可变速率和多种协议的方法
公开(公告)号：US07324548B2
公开(公告)日：2008-01-29
申请号：US10355472
申请日：2003-01-31
申请人： Vikram Natarajan , Kang Xiao , Mario Caresosa , Jay Proano , David Chung , Afshin Momtaz , Randy Stolaruk , Xin Wang , Namik Kocaman
发明人： Vikram Natarajan , Kang Xiao , Mario Caresosa , Jay Proano , David Chung , Afshin Momtaz , Randy Stolaruk , Xin Wang , Namik Kocaman
IPC分类号： H04J3/16 , H04J3/22 , H04J14/00 , H04B10/00
CPC分类号： H04Q11/0478 , H04J3/04 , H04J3/0685 , H04J3/1611 , H04J2203/0046 , H04J2203/0067 , H04J2203/0082 , H04J2203/0089 , Y10S370/907
摘要： Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.
摘要翻译：本发明是一种多速率收发器，其中可以以第一数据速率接收数据并以第二数据速率发送数据。收发器装置包括用于以一个数据速率接收能够将数据从第一速率映射到第二速率的映射器的数据的第一接口和用于以第二数据速率发送数据的第二接口。

5. 发明申请

US20050271169A1 High speed receive equalizer architecture 有权
标题翻译：高速接收均衡器架构
公开(公告)号：US20050271169A1
公开(公告)日：2005-12-08
申请号：US10880959
申请日：2004-06-30
申请人： Afshin Momtaz , Mario Caresosa , David Chung , Davide Tonietto , Guangming Yin , Bruce Currivan , Thomas Kolze , Ichiro Fujimori
发明人： Afshin Momtaz , Mario Caresosa , David Chung , Davide Tonietto , Guangming Yin , Bruce Currivan , Thomas Kolze , Ichiro Fujimori
IPC分类号： H03G3/30 , H03L7/091 , H04L7/02 , H04L7/033 , H04L25/03 , H04L27/08
CPC分类号： H04L7/033 , H03G3/3084 , H03L7/091 , H04L25/03057 , H04L2025/03375 , H04L2025/03617
摘要： Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.
摘要翻译：在高速通信接收机中提供均衡，其包括各种方面的自动增益控制输入级，判决反馈均衡器，时钟和数据恢复电路以及均衡控制电路。自动增益控制级可以包括具有可调节带宽的连续时间滤波器。阈值调整信号可以应用于自动增益控制级的输出。均衡控制电路可以在数字域中实现并且以比数据路径更低的时钟速度工作。

6. 发明申请

US20080130679A1 TRANSCEIVER SYSTEM AND METHOD SUPPORTING VARIABLE RATES AND MULTIPLE PROTOCOLS 审中-公开
标题翻译：收支系统和支持可变利率和多项协议的方法
公开(公告)号：US20080130679A1
公开(公告)日：2008-06-05
申请号：US11933881
申请日：2007-11-01
申请人： Vikram Natarajan , Kang Xiao , Mario Caresosa , Jay Proano , David Chung , Afshin Momtaz , Randy Stolaruk , Xin Wang , Namik Kocaman
发明人： Vikram Natarajan , Kang Xiao , Mario Caresosa , Jay Proano , David Chung , Afshin Momtaz , Randy Stolaruk , Xin Wang , Namik Kocaman
IPC分类号： H04J3/16 , H04J3/22 , H04B10/00 , H04J14/00
CPC分类号： H04Q11/0478 , H04J3/04 , H04J3/0685 , H04J3/1611 , H04J2203/0046 , H04J2203/0067 , H04J2203/0082 , H04J2203/0089 , Y10S370/907
摘要： Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.
摘要翻译：本发明是一种多速率收发器，其中可以以第一数据速率接收数据并以第二数据速率发送数据。收发器装置包括用于以一个数据速率接收能够将数据从第一速率映射到第二速率的映射器的数据的第一接口和用于以第二数据速率发送数据的第二接口。

7. 发明授权

US07974337B2 High speed receive equalizer architecture 有权
标题翻译：高速接收均衡器架构
公开(公告)号：US07974337B2
公开(公告)日：2011-07-05
申请号：US12606751
申请日：2009-10-27
申请人： Afshin Momtaz , Mario Caresosa , David Kyong-Sik Chung , Davide Tonietto , Guangming Yin , Bruce Currivan , Thomas Kolze , Ichiro Fujimori
发明人： Afshin Momtaz , Mario Caresosa , David Kyong-Sik Chung , Davide Tonietto , Guangming Yin , Bruce Currivan , Thomas Kolze , Ichiro Fujimori
IPC分类号： H03H7/30
CPC分类号： H04L7/033 , H03G3/3084 , H03L7/091 , H04L25/03057 , H04L2025/03375 , H04L2025/03617
摘要： Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.
摘要翻译：公开了各种示例性实施例。根据示例实施例，设备可以包括连续时间滤波器，判决反馈均衡器，时钟和数据恢复电路以及适配电路。适配电路可以被配置为通过基于均衡数据信号的均方误差调整延迟调整信号来根据至少一个抖动算法来适应均衡。

8. 发明授权

US06864752B2 Configurable voltage controlled oscillator system and method 有权
公开(公告)号：US06864752B2
公开(公告)日：2005-03-08
申请号：US10444022
申请日：2003-05-22
申请人： Mario Caresosa , Namik Kocaman , Afshin Momtaz
发明人： Mario Caresosa , Namik Kocaman , Afshin Momtaz
IPC分类号： H03L7/099 , H03L7/18 , H04J3/04 , H04J3/06 , H04Q11/04
CPC分类号： H04J3/0685 , H03L7/099 , H03L7/0998 , H03L7/18 , H04J3/04 , H04J3/047 , H04J2203/0089
摘要： A phase lock loop with multiple divider paths is presented herein. The phase lock loop can be used to provide a wide range of frequencies. The phase lock loop can also be used as a portion of a clock multiplier unit or a clock data and recovery unit.

9. 发明授权

US07522847B2 Continuous time filter-decision feedback equalizer architecture for optical channel equalization 失效
标题翻译：用于光信道均衡的连续时间滤波器 - 判决反馈均衡器架构
公开(公告)号：US07522847B2
公开(公告)日：2009-04-21
申请号：US10774724
申请日：2004-02-09
申请人： Afshin Momtaz , Mario Caresosa
发明人： Afshin Momtaz , Mario Caresosa
IPC分类号： H04B10/00
CPC分类号： H04B10/66 , H04L25/03038 , H04L25/03057 , H04L2025/0349
摘要： A communication system having a transmitter transmits an information signal over a communication media and a receiver coupled to the communication media receives the transmitted information signal. The receiver includes a continuous time filter having an adjustable bandwidth for linearly equalizing the transmitted information signal as a function of the adjustable bandwidth. A decision feedback equalizer coupled to the continuous time filter then reduces inter-symbol interference in the filtered information signal.
摘要翻译：具有发射机的通信系统通过通信介质发送信息信号，并且耦合到通信媒体的接收机接收所发送的信息信号。接收机包括具有可调节带宽的连续时间滤波器，用于作为可调节带宽的函数线性地均衡所发送的信息信号。耦合到连续时间滤波器的判决反馈均衡器然后减少滤波信息信号中的符号间干扰。

10. 发明申请

US20050248396A1 Novel VGA-CTF combination cell for 10 GB/S serial data receivers 失效
标题翻译：用于10 GB / S串行数据接收器的新型VGA-CTF组合单元
公开(公告)号：US20050248396A1
公开(公告)日：2005-11-10
申请号：US10841766
申请日：2004-05-07
申请人： Mario Caresosa , Afshin Momtaz , Guangming Yin
发明人： Mario Caresosa , Afshin Momtaz , Guangming Yin
IPC分类号： H03F3/45 , H03G1/00
CPC分类号： H03G1/007 , H03F3/45188 , H03F3/45197 , H03F2203/45504 , H03F2203/45638 , H03G1/0029 , H03G1/0088
摘要： An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage. The control voltage is applied to the gate terminal of the at least one first transistor, and the control voltage is applied to the gate terminal of the at least one second transistor through the gate switch.
摘要翻译：输入处理电路包括分别用于接收第一和第二输入信号的差分对的第一和第二输入晶体管。至少一个电阻耦合在第一和第二输入晶体管的第一端之间。输入处理电路包括可变增益放大器（VGA）电路。至少一个第一晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。至少一个第二晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。栅极开关耦合到至少一个第二晶体管的栅极端子。所述至少一个第一晶体管和所述至少一个第二晶体管响应于控制电压调整所述输入处理电路的增益。控制电压被施加到至少一个第一晶体管的栅极端子，并且通过栅极开关将控制电压施加到至少一个第二晶体管的栅极端子。

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