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1. 发明申请

US20090286387A1 Modulation of Tantalum-Based Electrode Workfunction 审中-公开
标题翻译：钽电极工作功能的调制
公开(公告)号：US20090286387A1
公开(公告)日：2009-11-19
申请号：US12122178
申请日：2008-05-16
申请人： David C. Gilmer , Srikanth B. Samavedam , James K. Schaeffer , Voon-Yew Thean
发明人： David C. Gilmer , Srikanth B. Samavedam , James K. Schaeffer , Voon-Yew Thean
IPC分类号： H01L21/28 , H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4975
摘要： A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (14) over a gate dielectric layer (12) and then selectively introducing nitrogen into the portions of the first conductive layer (14) in the PMOS device region (1), either by annealing (42) a nitrogen-containing diffusion layer (22) formed in the PMOS device region (1) or by performing an ammonia anneal process (82) while the NMOS device region (2) is masked. By introducing nitrogen into the first conductive layer (14), the work function is modulated toward PMOS band edge.
摘要翻译：一种半导体工艺和装置，通过在栅介质层（12）上形成第一导电层（14）制造金属栅电极，然后选择性地将氮引入PMOS器件区域（1）中的第一导电层（14）的部分），通过在形成于PMOS器件区域（1）中的含氮扩散层（22）退火（42），或者在NMOS器件区域（2）被掩蔽的同时执行氨退火工艺（82）。通过将氮引入到第一导电层（14）中，功函数被调制到PMOS带边缘。

2. 发明申请

US20080001202A1 A METHOD OF MAKING METAL GATE TRANSISTORS 失效
标题翻译：制造金属栅极晶体管的方法
公开(公告)号：US20080001202A1
公开(公告)日：2008-01-03
申请号：US11427980
申请日：2006-06-30
申请人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
发明人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
IPC分类号： H01L29/94
CPC分类号： H01L27/1203 , H01L21/28105 , H01L21/823842 , H01L21/84 , H01L29/4966 , H01L29/517
摘要： A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.
摘要翻译：半导体器件具有在高K栅极电介质上的具有三个导电层的栅极。第一层基本上是无氧的。响应于随后的热处理，功函数被第二导电层调制到期望的功函数。第二层是导电含氧金属。具有足够的第一层的厚度，氧从第二层穿过第一层的最小穿透而不利地影响栅极电介质，但充分渗入氧气以将功函数改变到更理想的水平。金属的第三层沉积在第二层上。多晶硅层沉积在第三层上。第三层防止多晶硅层和含氧层一起反应。

3. 发明授权

US07683439B2 Semiconductor device having a metal carbide gate with an electropositive element and a method of making the same 有权
标题翻译：具有具有正电性单元的金属碳化物栅极的半导体器件及其制造方法
公开(公告)号：US07683439B2
公开(公告)日：2010-03-23
申请号：US11685027
申请日：2007-03-12
申请人： Srikanth B. Samavedam , David C. Gilmer , Mark V. Raymond , James K. Schaeffer
发明人： Srikanth B. Samavedam , David C. Gilmer , Mark V. Raymond , James K. Schaeffer
IPC分类号： H01L27/088
CPC分类号： H01L29/4966 , H01L21/28088 , H01L29/4908 , H01L29/4958
摘要： A semiconductor device structure is formed over a semiconductor substrate and has a gate dielectric over the semiconductor substrate and a gate over the gate dielectric. The gate, at an interface with the gate dielectric, comprises a transition metal, carbon, and an electropositive element. The transition metal comprises one of group consisting of tantalum, titanium, hafnium, zirconium, molybdenum, and tungsten. The electropositive element comprises one of a group consisting of a Group IIA element, a Group IIIB element, and lanthanide series element.
摘要翻译：半导体器件结构形成在半导体衬底之上并且在半导体衬底上方具有栅极电介质，并且在栅极电介质上方具有栅极。在与栅极电介质的界面处的栅极包含过渡金属，碳和正电性元素。过渡金属由钽，钛，铪，锆，钼和钨组成。正电荷元素包括由IIA族元素，IIIB族元素和镧系元素组成的组中的一种。

4. 发明授权

US07655550B2 Method of making metal gate transistors 失效
标题翻译：制造金属栅晶体管的方法
公开(公告)号：US07655550B2
公开(公告)日：2010-02-02
申请号：US11427980
申请日：2006-06-30
申请人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
发明人： James K. Schaeffer , David C. Gilmer , Mark V. Raymond , Philip J. Tobin , Srikanth B. Samavedam
IPC分类号： H01L21/4763
CPC分类号： H01L27/1203 , H01L21/28105 , H01L21/823842 , H01L21/84 , H01L29/4966 , H01L29/517
摘要： A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.
摘要翻译：半导体器件具有在高K栅极电介质上的具有三个导电层的栅极。第一层基本上是无氧的。响应于随后的热处理，功函数被第二导电层调制到期望的功函数。第二层是导电含氧金属。具有足够的第一层的厚度，氧从第二层穿过第一层的最小穿透而不利地影响栅极电介质，但充分渗入氧气以将功函数改变到更理想的水平。金属的第三层沉积在第二层上。多晶硅层沉积在第三层上。第三层防止多晶硅层和含氧层一起反应。

5. 发明申请

US20080224185A1 SEMICONDUCTOR DEVICE HAVING A METAL CARBIDE GATE WITH AN ELECTROPOSITIVE ELEMENT AND A METHOD OF MAKING THE SAME 有权
标题翻译：具有电镀元件的金属碳化硅栅的半导体器件及其制造方法
公开(公告)号：US20080224185A1
公开(公告)日：2008-09-18
申请号：US11685027
申请日：2007-03-12
申请人： Srikanth B. Samavedam , David C. Gilmer , Mark V. Raymond , James K. Schaeffer
发明人： Srikanth B. Samavedam , David C. Gilmer , Mark V. Raymond , James K. Schaeffer
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/4966 , H01L21/28088 , H01L29/4908 , H01L29/4958
摘要： A semiconductor device structure is formed over a semiconductor substrate and has a gate dielectric over the semiconductor substrate and a gate over the gate dielectric. The gate, at an interface with the gate dielectric, comprises a transition metal, carbon, and an electropositive element. The transition metal comprises one of group consisting of tantalum, titanium, hafnium, zirconium, molybdenum, and tungsten. The electropositive element comprises one of a group consisting of a Group IIA element, a Group IIIB element, and lanthanide series element.
摘要翻译：半导体器件结构形成在半导体衬底之上并且在半导体衬底上方具有栅极电介质，并且在栅极电介质上方具有栅极。在与栅极电介质的界面处的栅极包含过渡金属，碳和正电性元素。过渡金属由钽，钛，铪，锆，钼和钨组成。正电荷元素包括由IIA族元素，IIIB族元素和镧系元素组成的组中的一种。

6. 发明申请

US20090291540A1 CMOS Process with Optimized PMOS and NMOS Transistor Devices 有权
标题翻译： CMOS工艺与优化的PMOS和NMOS晶体管器件
公开(公告)号：US20090291540A1
公开(公告)日：2009-11-26
申请号：US12125855
申请日：2008-05-22
申请人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
发明人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/1054 , H01L29/6659 , H01L29/66636 , H01L29/66651 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译：半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34）以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

7. 发明授权

US08003454B2 CMOS process with optimized PMOS and NMOS transistor devices 有权
标题翻译： CMOS工艺具有优化的PMOS和NMOS晶体管器件
公开(公告)号：US08003454B2
公开(公告)日：2011-08-23
申请号：US12125855
申请日：2008-05-22
申请人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
发明人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
IPC分类号： H01L21/336 , H01L21/337
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/1054 , H01L29/6659 , H01L29/66636 , H01L29/66651 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译：半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34）以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

8. 发明申请

US20090289280A1 Method for Making Transistors and the Device Thereof 审中-公开
标题翻译：制造晶体管及其器件的方法
公开(公告)号：US20090289280A1
公开(公告)日：2009-11-26
申请号：US12125853
申请日：2008-05-22
申请人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
发明人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming channel orientation PMOS transistors (34) with enhanced hole mobility in the channel region of a transistor by epitaxially growing a bi-axially stressed silicon germanium channel region layer (22), alone or in combination with an underlying silicon carbide layer (86), prior to forming a PMOS gate structure (36) overlying the channel region layer, and then depositing a neutral (53) or compressive (55) contact etch stop layer over the PMOS gate structure. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译：半导体工艺和装置包括通过外延生长双轴向应力的硅锗沟道区域层（22）来形成具有增强的晶体管沟道区中的空穴迁移率的<100>沟道取向PMOS晶体管（34），单独或与在形成覆盖在沟道区域层上的PMOS栅极结构（36）之前，然后在PMOS栅极结构上沉积中性（53）或压缩（55）接触蚀刻停止层之后的底层碳化硅层（86）。也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

9. 发明授权

US07445976B2 Method of forming a semiconductor device having an interlayer and structure therefor 有权
标题翻译：形成具有中间层的半导体器件及其结构的方法
公开(公告)号：US07445976B2
公开(公告)日：2008-11-04
申请号：US11420525
申请日：2006-05-26
申请人： James K. Schaeffer , Rama I. Hegde , Srikanth B. Samavedam
发明人： James K. Schaeffer , Rama I. Hegde , Srikanth B. Samavedam
IPC分类号： H01L21/00
CPC分类号： H01L21/823857 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L29/4966 , H01L29/517
摘要： A stack located over a substrate. The stack includes a layer between a dielectric layer and a metal layer. The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example the control electrode stack is a gate stack for a MOSFET. In one example, the layer includes aluminum fluoride.
摘要翻译：位于衬底上方的堆叠。堆叠包括介电层和金属层之间的层。该层包括卤素和金属。在一个实施方案中，卤素是氟。在一个实施例中，堆叠是用于晶体管的控制电极堆叠。在一个示例中，控制电极堆叠是用于MOSFET的栅极堆叠。在一个实例中，该层包括氟化铝。

10. 发明授权

US08178401B2 Method for fabricating dual-metal gate device 有权
标题翻译：双金属栅极器件制造方法
公开(公告)号：US08178401B2
公开(公告)日：2012-05-15
申请号：US11530058
申请日：2006-09-08
申请人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
发明人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.
摘要翻译：一种制造包括由异型金属形成的双金属栅极的MOS晶体管的方法。诸如HfO 2的栅极电介质（34）沉积在半导体衬底上。牺牲层（35）接着沉积在栅极电介质上。牺牲层被图案化，使得衬底的第一（pMOS，例如）区域（32）上的栅极电介质被暴露，并且衬底的第二（nMOS，例如）区域（33）上的栅极电介质继续是受牺牲层保护。第一栅极导体材料（51）沉积在剩余的牺牲区域上并暴露在栅极电介质上。图案化第一栅极导体材料，使得衬底的第二区域上方的第一栅极导体材料被蚀刻掉。第二区域上的牺牲层防止在去除第一栅极导体材料时损坏下面的介电材料。

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