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1. 发明授权

US5266933A Method and apparatus for displaying a screen separator line 失效
标题翻译：用于显示屏幕分离线的方法和装置
公开(公告)号：US5266933A
公开(公告)日：1993-11-30
申请号：US58805
申请日：1993-05-04
申请人： David C. Frank , Shigeru Matsubara , Hiroshi Satoh , Stephen P. Thompson
发明人： David C. Frank , Shigeru Matsubara , Hiroshi Satoh , Stephen P. Thompson
IPC分类号： G09G1/00 , G09G1/14
CPC分类号： G09G1/007
摘要： Method and apparatus for displaying a horizontal screen separator line between two screen areas. A first step operates a display screen controller (12) in a split screen mode of operation so as to display a first screen area (3) at an upper portion of a display screen (18) and a second screen area (4) at a lower portion of the display screen. The step of operating further includes a step of reading data from a screen memory (42) and displaying rows of corresponding alphanumeric characters. Each character is displayed as a plurality of image pixels arranged along a first number of horizontal scan lines. A further step displays a horizontal visual separator (2) between a last row of the first screen area and a first row of the second screen area. The step of displaying the horizontal visual separator includes the steps of (a) reading data from the screen memory and beginning a display of a row of corresponding visual separator characters; and (b) terminating the display of the row of corresponding visual separator characters after displaying a second number of horizontal scan lines that is less than the first number of horizontal scan lines.
摘要翻译：用于在两个屏幕区域之间显示水平屏幕分离线的方法和装置。第一步骤以分屏操作模式操作显示屏幕控制器（12），以便在显示屏幕（18）的上部和第二屏幕区域（4）处显示第一屏幕区域（3）显示屏的下部。操作步骤还包括从屏幕存储器（42）读取数据并显示相应字母数字字符的行的步骤。每个字符被显示为沿着第一数量的水平扫描线布置的多个图像像素。另一步骤在第一屏幕区域的最后一行和第二屏幕区域的第一行之间显示水平视觉分离器（2）。显示水平视觉分离器的步骤包括以下步骤：（a）从屏幕存储器读取数据并开始显示一行相应的视觉分离符字符; 以及（b）在显示小于第一数量的水平扫描线的第二数量的水平扫描线之后终止相应的可视分离符字符行的显示。

2. 发明授权

US09104593B2 Filtering requests for a translation lookaside buffer 有权
标题翻译：筛选翻译后备缓冲区的请求
公开(公告)号：US09104593B2
公开(公告)日：2015-08-11
申请号：US13714466
申请日：2012-12-14
申请人： Stephen P. Thompson
发明人： Stephen P. Thompson
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/681
摘要： The present application describes a method and apparatus for filtering requests to a translation lookaside buffer (TLB). Some embodiments of the method include receiving, from a first translation lookaside buffer (TLB), an indication of a first virtual address associated with a request to a second TLB for a page table entry in response to a miss in the first TLB. Some embodiments of the method also include filtering the request based on a comparison of the first virtual address and one or more second virtual addresses associated with one or more previous requests to the second TLB.
摘要翻译：本申请描述了用于将请求过滤到翻译后备缓冲器（TLB）的方法和装置。该方法的一些实施例包括响应于第一TLB中的未命中从第一翻译后备缓冲器（TLB）接收与针对页表条目的第二TLB的请求相关联的第一虚拟地址的指示。该方法的一些实施例还包括基于第一虚拟地址与与一个或多个先前请求相关联的一个或多个第二虚拟地址与第二TLB的比较来过滤该请求。

3. 发明授权

US08856451B2 Method and apparatus for adapting aggressiveness of a pre-fetcher 有权
标题翻译：用于调整预取器的侵略性的方法和装置
公开(公告)号：US08856451B2
公开(公告)日：2014-10-07
申请号：US12869163
申请日：2010-08-26
申请人： Stephen P. Thompson , Tarun Nakra
发明人： Stephen P. Thompson , Tarun Nakra
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： The present invention provides a method and apparatus for adapting aggressiveness of a pre-fetcher in a processor-based system. One embodiment includes modifying a rate for pre-fetching data from a memory into one or more caches by comparing a first address of a memory access request to addresses in an address window that includes one or more previously fetched addresses and one or more addresses to be fetched.
摘要翻译：本发明提供了一种用于在基于处理器的系统中调整预取器的侵略性的方法和装置。一个实施例包括通过将存储器访问请求的第一地址与包括一个或多个先前提取的地址和一个或多个地址的地址窗口中的地址进行比较来修改用于将数据从存储器预取到一个或多个高速缓存的速率取得

4. 发明申请

US20130346703A1 DATA CACHE PREFETCH THROTTLE 有权
公开(公告)号：US20130346703A1
公开(公告)日：2013-12-26
申请号：US13528302
申请日：2012-06-20
申请人： Donald W. McCauley , Stephen P. Thompson
发明人： Donald W. McCauley , Stephen P. Thompson
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024 , G06F2212/6026
摘要： The present invention provides a method and apparatus for throttling prefetch requests for a cache. One embodiment of the method includes selecting a sequence of relative addresses for prefetching data from a memory into lines of a cache in response to detecting a cache miss to a first address. The sequence of relative addresses is determined relative to the first address. This embodiment of the method also includes issuing a prefetch request for data from a memory address indicated by one of the sequence of relative addresses when at least one previous prefetch stream accessed prefetched data associated with this one of the sequence of relative addresses.
摘要翻译：本发明提供了一种用于节流缓存的预取请求的方法和装置。该方法的一个实施例包括从响应于检测到第一地址的高速缓存未命中而选择用于将数据从存储器预取到高速缓存行的相对地址序列。相对地址的序列相对于第一个地址确定。该方法的该实施例还包括当至少一个先前预取流访问与该相对地址序列中的一个相关联的预取数据时，从由相对地址序列之一指示的存储器地址中发出数据的预取请求。

5. 发明申请

US20080052467A1 System for restricted cache access during information transfers and method thereof 审中-公开
标题翻译：在信息传输期间限制缓存访问的系统及其方法
公开(公告)号：US20080052467A1
公开(公告)日：2008-02-28
申请号：US11510370
申请日：2006-08-25
申请人： Stephen P. Thompson
发明人： Stephen P. Thompson
IPC分类号： G06F12/00 , G06F12/14
CPC分类号： G06F12/123 , G06F12/0864 , G06F12/1425
摘要： Instructions involving a relatively significant information transfer or a particular type of information transfer via a cache, or specified address ranges within cache causing a cache miss result in the application of a restricted access policy to control access to one or more partitions of the cache so as to reduce or prevent the overwriting of information that is expected to be subsequently used by the cache or by a processor. A processor or other system component may assert a signal which is utilized to select between one or more access policies based on instructions or their type so that an access may be applied to control access to one or more ways of the cache during the information transfer operation associated with the instruction. Similarly, a cache way select module may select between one or more access policies based on an address range so that an access policy may be applied to control access to one or more ways of the cache during access to a specific range of memory. The access policy typically represents an access restriction to particular cache partitions, such as a restriction to one or more particular cache ways or one or more particular cache lines.
摘要翻译：涉及相对较重要的信息传输或特定类型的通过缓存的信息传输的指令或导致高速缓存未命中的高速缓存中的指定地址范围导致应用受限访问策略来控制对高速缓存的一个或多个分区的访问，以便以减少或防止重写由缓存或处理器随后使用的信息。处理器或其他系统组件可以基于指令或其类型来断言用于在一个或多个访问策略之间进行选择的信号，使得可以应用访问以在信息传递操作期间控制对高速缓存的一种或多种方式的访问与指令相关联。类似地，高速缓存方式选择模块可以基于地址范围在一个或多个访问策略之间进行选择，使得访问策略可以被应用于在访问特定存储器范围期间控制对高速缓存的一种或多种方式的访问。访问策略通常表示对特定高速缓存分区的访问限制，例如对一个或多个特定高速缓存路径的限制或一个或多个特定高速缓存行。

6. 发明授权

US5444855A System for guaranteed CPU bus access by I/O devices monitoring separately predetermined distinct maximum non CPU bus activity and inhibiting I/O devices thereof 失效
标题翻译：用于I / O设备保证CPU总线访问的系统分别监视预定的不同的最大非CPU总线活动并禁止其I / O设备
公开(公告)号：US5444855A
公开(公告)日：1995-08-22
申请号：US870581
申请日：1992-04-17
申请人： Stephen P. Thompson
发明人： Stephen P. Thompson
IPC分类号： G06F13/362 , G06F13/372 , G06F13/36
CPC分类号： G06F13/372
摘要： A method and system for controlling access to a system bus in a computer system is provided. The system devices include a central processing unit, a memory controller for controlling access to system memory, and at least one input/output device having a coprocessor incorporated therein. The system bus electrically connects the system devices. Any one of the system devices may serve as a bus master of the system bus at any one time when communicating over the bus with each other or with system memory. Each of the at least one input/output device incorporates control logic therein for (i) monitoring bus activity to calculate the bus mastering time during which the memory controller and the at least one input/output device control the bus, and (ii) outputting an inhibit signal which denies access to the bus by the at least one input/output device if the calculated bus mastering time is equal to or greater than a predetermined bus mastering time period.
摘要翻译：提供了一种用于控制计算机系统中对系统总线的访问的方法和系统。系统设备包括中央处理单元，用于控制对系统存储器的访问的存储器控制器以及其中并入有协处理器的至少一个输入/输出设备。系统总线电气连接系统设备。任何一个系统设备可以在通过总线与彼此或与系统存储器通信时的任何一个时间用作系统总线的总线主机。所述至少一个输入/输出设备中的每一个都包括其中的控制逻辑，用于（i）监视总线活动以计算存储器控制器和至少一个输入/输出设备控制总线的总线主控时间，以及（ii）输出禁止信号，如果所计算的总线主控时间等于或大于预定的总线控制时间段，则禁止由至少一个输入/输出设备访问总线。

7. 发明授权

US5001652A Memory arbitration for video subsystems 失效
标题翻译：视频子系统的内存仲裁
公开(公告)号：US5001652A
公开(公告)日：1991-03-19
申请号：US363344
申请日：1989-06-06
申请人： Stephen P. Thompson
发明人： Stephen P. Thompson
IPC分类号： G09G1/16 , G09G5/00
CPC分类号： G09G5/001
摘要： A video subsystem has a CRT (cathode ray tube) display, video controller and video memory for CRT data which requires access by the controller and a CPU (control processing unit). The subsystem monitors activity of the CRT screen display and the video controller and anytime CRT screen display is not required regardless of the time of occurrence, the CPU is allowed to have access to the video memory during the cycle or cycles in which such inactivity of display occurs. A guaranteed minimum number of cycles is assured for access of the video memory by the CPU using a fixed access sequence during the display periods of a high speed mode and shifting to an arbitration strategy to allow CPU access to occur during non-display times of the high speed mode so that the CPU can acquire more cycles to reduce any backlog of requests as necessary. In a low speed mode, the subsystem automatically changes strategy so that arbitration occurs both during display and non-display periods so that the CPU can acquire memory cycles on an as needed basis.
摘要翻译：视频子系统具有需要由控制器和CPU（控制处理单元）访问的CRT数据的CRT（阴极射线管）显示器，视频控制器和视频存储器。该子系统监视CRT屏幕显示器和视频控制器的活动，并且无论何时发生CRT时间，CRT屏幕显示都不需要，CPU允许在循环期间访问视频存储器，或者在显示器的这种不活动状态的周期内发生。在高速模式的显示周期期间，确保CPU使用固定访问序列访问视频存储器的保证最小数量，并转移到仲裁策略，以允许在非显示时间内进行CPU访问高速模式，使得CPU可以获得更多的周期，以减少必要的积压的请求。在低速模式下，子系统自动更改策略，以便在显示和非显示周期期间发生仲裁，以便CPU可以根据需要获取内存周期。

8. 发明申请

US20120096226A1 TWO LEVEL REPLACEMENT SCHEME OPTIMIZES FOR PERFORMANCE, POWER, AND AREA 审中-公开
标题翻译：两级替代方案优化性能，功率和面积
公开(公告)号：US20120096226A1
公开(公告)日：2012-04-19
申请号：US12906936
申请日：2010-10-18
申请人： Stephen P. Thompson , Robert Krick , Tarun Nakra
发明人： Stephen P. Thompson , Robert Krick , Tarun Nakra
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/121 , Y02D10/13
摘要： A two-level replacement scheme is provided for selecting an entry in a cache memory to replace when a cache miss takes place and the memory is full. The scheme divides the tags associated with each memory location of the cache into two or more groups, each group relating to a subset of memory locations of the cache. The scheme uses a first algorithm to select one of the groups and passes the tags for the group through a second algorithm. The second algorithm produces a local index which, when combined with a group index, produces a replacement index that identifies a memory location in the cache to replace.
摘要翻译：提供两级替换方案，用于选择高速缓冲存储器中的条目以替代发生高速缓存未命中并且存储器已满。该方案将与高速缓存的每个存储器位置相关联的标签划分成两个或更多个组，每个组涉及高速缓存的存储器位置的子集。该方案使用第一种算法来选择一个组，并通过第二种算法传递该组的标签。第二种算法产生本地索引，当与组索引组合时，产生一个替换索引，该索引标识要替换的高速缓存中的内存位置。

9. 发明申请

US20120054448A1 METHOD AND APPARATUS FOR ADAPTING AGGRESSIVENESS OF A PRE-FETCHER 有权
标题翻译：用于适应预充电器的抗腐蚀性的方法和装置
公开(公告)号：US20120054448A1
公开(公告)日：2012-03-01
申请号：US12869163
申请日：2010-08-26
申请人： Stephen P. Thompson , Tarun Nakra
发明人： Stephen P. Thompson , Tarun Nakra
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： The present invention provides a method and apparatus for adapting aggressiveness of a pre-fetcher in a processor-based system. One embodiment includes modifying a rate for pre-fetching data from a memory into one or more caches by comparing a first address of a memory access request to addresses in an address window that includes one or more previously fetched addresses and one or more addresses to be fetched.
摘要翻译：本发明提供了一种用于在基于处理器的系统中调整预取器的侵略性的方法和装置。一个实施例包括通过将存储器访问请求的第一地址与包括一个或多个先前提取的地址和一个或多个地址的地址窗口中的地址进行比较来修改用于将数据从存储器预取到一个或多个高速缓存的速率取得

10. 发明授权

US07536510B1 Hierarchical MRU policy for data cache 失效
标题翻译：数据缓存的分层MRU策略
公开(公告)号：US07536510B1
公开(公告)日：2009-05-19
申请号：US11242578
申请日：2005-10-03
申请人： Stephen P. Thompson
发明人： Stephen P. Thompson
IPC分类号： G06F12/00
CPC分类号： G06F12/0864
摘要： A cache read request is received at a cache comprising a plurality of data arrays, each of the data arrays comprising a plurality of ways. Cache line data from each most recently used way of each of the plurality of data arrays is selected in response to the cache read request and selecting a first data of the received cache line data from the most recently used way of the cache. An execution of an instruction is stalled if data identified by the cache read request is not present in the cache line data from the most recently used way of the cache. A second data from a most recently used way of one of the plurality of data arrays other than the most recently used data array is selected as comprising data identified by the cache read request. The second data is provided for use during the execution of the instruction.
摘要翻译：在包括多个数据阵列的高速缓存中接收高速缓存读取请求，每个数据阵列包括多个方式。响应于高速缓存读取请求选择来自多个数据阵列中的每一个的每个最近使用的方式的高速缓存线数据，并且从最近使用的高速缓存的方式中选择所接收的高速缓存线数据的第一数据。如果高速缓存读取请求所标识的数据不是从最近使用的高速缓存的方式存在于高速缓存线数据中，则停止执行指令。选择除了最近使用的数据阵列之外的多个数据阵列之一的最近使用的方式的第二数据包括由高速缓存读取请求标识的数据。第二个数据被提供用于在执行指令期间使用。

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