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1. 发明授权

US5872990A Reordering of memory reference operations and conflict resolution via rollback in a multiprocessing environment 失效
标题翻译：通过多处理环境中的回滚重新排序内存引用操作和冲突解决
公开(公告)号：US5872990A
公开(公告)日：1999-02-16
申请号：US779071
申请日：1997-01-07
申请人： David Arnold Luick , John Christopher Willis , Philip Braun Winterfield
发明人： David Arnold Luick , John Christopher Willis , Philip Braun Winterfield
IPC分类号： G06F9/38 , G06F9/45 , G06F9/46
CPC分类号： G06F9/52 , G06F8/445 , G06F9/3834 , G06F9/3863
摘要： Compile and/or run time instruction scheduling is used in a multiprocessing system to reorder memory access instructions such that a strongly consistent programming model is emulated in a fashion transparent to the programmer. The multiprocessing system detects potential shared memory conflicts, avoiding these conflicts by restarting operation of the affected processing unit at a predetermined previous state, previously archived in a rollback register set, and resuming instruction execution from that state.
摘要翻译：在多处理系统中使用编译和/或运行时指令调度来重新排序存储器访问指令，使得以对编程器透明的方式来模拟强烈一致的编程模型。多处理系统检测潜在的共享内存冲突，通过在预先存储在回滚寄存器组中的预定先前状态下重新启动受影响的处理单元的操作，以及从该状态恢复指令执行来避免这些冲突。

2. 发明授权

US6088769A Multiprocessor cache coherence directed by combined local and global tables 失效
标题翻译：由局部和全局表组合引导的多处理器缓存一致性
公开(公告)号：US6088769A
公开(公告)日：2000-07-11
申请号：US724628
申请日：1996-10-01
申请人： David Arnold Luick , John Christopher Willis , Philip Braun Winterfield
发明人： David Arnold Luick , John Christopher Willis , Philip Braun Winterfield
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/082 , G06F12/0826
摘要： A method and apparatus for maintaining coherence between shared data stored within a plurality of memory devices, each memory device residing in a different node within a tightly coupled multiprocessor system. Each node includes a "local coherence unit" and an associated processor. A cache unit is associated with each memory/processor pair. Each local coherence unit maintains a table which indicates whether the most current copy of data stored within the node resides in the local memory, in the local cache, or in a non-local cache. The present invention includes a "global coherence" unit coupled to each node via the logical interconnect. The global coherence unit includes a interconnect monitoring device and a global coherence table. When data which resides within the memory of a first node is transferred to a second node, the interconnect monitoring device updates the global coherence table to indicate that the data is being shared. The global coherence table also preferably indicates in which node a copy of the most current data resides.
摘要翻译：一种用于维持存储在多个存储设备中的共享数据之间的一致性的方法和装置，每个存储器设备驻留在紧密耦合的多处理器系统内的不同节点中。每个节点包括“局部相干单元”和相关联的处理器。高速缓存单元与每个存储器/处理器对相关联。每个局部相干单元维护表，该表指示存储在节点内的最新数据副本是否驻留在本地存储器，本地高速缓存中或非本地高速缓存中。本发明包括通过逻辑互连耦合到每个节点的“全局相干”单元。全局相干单元包括互连监视设备和全局相干表。当驻留在第一节点的存储器内的数据被传送到第二节点时，互连监视设备更新全局一致性表以指示正在共享数据。全局一致性表还优选地指示哪个节点存在最新数据的副本。

3. 发明授权

US06233599B1 Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers 失效
标题翻译：通过分区和重叠寄存器在计算机上改进多线程操作的装置和方法
公开(公告)号：US06233599B1
公开(公告)日：2001-05-15
申请号：US08890867
申请日：1997-07-10
申请人： George Wayne Nation , Robert N. Newshutz , John Christopher Willis
发明人： George Wayne Nation , Robert N. Newshutz , John Christopher Willis
IPC分类号： G06F900
CPC分类号： G06F9/462 , G06F9/30127 , G06F9/3851 , G06F9/5061
摘要： An apparatus and method for performing multithreaded operations includes partitioning the general purpose and/or floating point processor registers into register subsets, including overlapping register subsets, allocating the register subsets to the threads, and managing the register subsets during thread switching. Register overwrite buffers preserve thread resources in overlapping registers during the thread switching process. Thread resources are loaded into the corresponding register subsets or, when overlapping register subsets are employed, into either the corresponding register subset or the corresponding register overwrite buffer. A thread status register is utilized by a thread controller to keep track of READY/NOT-READY threads, the active thread, and whether single-thread or multithread operations are permitted. Furthermore, the registers in the register subsets include a thread identifier field to identify the corresponding thread. Register masks may also be used to identify which registers belong to the various register subsets.
摘要翻译：用于执行多线程操作的装置和方法包括将通用和/或浮点处理器寄存器划分为寄存器子集，包括重叠寄存器子集，将注册子集分配给线程，以及在线程切换期间管理寄存器子集。注册覆盖缓冲区会在线程切换过程中保留重叠寄存器中的线程资源。线程资源被加载到相应的寄存器子集中，或者当使用重叠的寄存器子集时，进入相应的寄存器子集或对应的寄存器重写缓冲器。线程控制器利用线程状态寄存器来跟踪READY / NOT-READY线程，活动线程以及是否允许单线程或多线程操作。此外，寄存器子集中的寄存器包括用于标识相应线程的线程标识符字段。寄存器掩码也可用于识别哪些寄存器属于各种寄存器子集。

4. 发明申请

US20100023308A1 METHOD FOR ACCELERATING SIMULATION PERFORMANCE AND INCREASING SIMULATION ACCURACY OF MODELS USING DYNAMIC SELECTION AND REPLACEMENT OF EXECUTABLE EMBODIMENTS WITH TEMPORALLY OPTIMAL FUNCTIONAL DETAIL AND SIMPLIFICATION 审中-公开
标题翻译：使用动态选择来提高模拟性能并提高模型的模拟精度的方法和替代具有临时性的最佳功能细节和简化的可执行实施例
公开(公告)号：US20100023308A1
公开(公告)日：2010-01-28
申请号：US12372014
申请日：2009-02-17
申请人： John Christopher Willis , Joshua Alan Johnson , Ruth Ann Betcher
发明人： John Christopher Willis , Joshua Alan Johnson , Ruth Ann Betcher
IPC分类号： G06G7/62
CPC分类号： G06F17/5027 , G06F17/5036
摘要： A method for increasing simulation speed is achieved by implementing a sequence of executable embodiments of digital, analog, mixed-signal or full-wave components are substituted during the process. The substituted embodiments represent more optimal instruction sequences, reconfigurable logic configurations or combinations thereof which may only be a valid representation of the model being simulated, subject to specific operating conditions.
摘要翻译：通过在该过程中替代数字，模拟，混合信号或全波分量的可执行实施例的序列来实现增加模拟速度的方法。替代的实施例表示更多的最优指令序列，可重构逻辑配置或其组合，其可以仅仅是正在被模拟的模型的有效表示，受特定的操作条件的限制。

5. 发明授权

US5860138A Processor with compiler-allocated, variable length intermediate storage 失效
标题翻译：具有编译器分配，可变长度中间存储的处理器
公开(公告)号：US5860138A
公开(公告)日：1999-01-12
申请号：US537556
申请日：1995-10-02
申请人： David Robert Engebretsen , Steven Lee Gregor , Mayan Moudgill , John Christopher Willis
发明人： David Robert Engebretsen , Steven Lee Gregor , Mayan Moudgill , John Christopher Willis
IPC分类号： G06F9/34 , G06F9/30 , G06F9/35 , G06F9/38 , G06F12/02 , G06F12/08 , G06F12/10 , G06F9/26
CPC分类号： G06F9/3013 , G06F9/35 , G06F9/383
摘要： A processor includes an alias unit having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries that consist of a base address in the processor memory to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor can optionally include a data cache and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.
摘要翻译：处理器包括具有在编译时分配用于可变大小的数据对象的高速存储器存储位置的别名单元。存储位置通过别名条目的表进行访问，该表由处理器存储器中的别名条目别名的基地址，别名条目中的字节数和指向别名的第一个字节的基址组成表示别名条目值的缓冲存储器。每个别名条目都从一个小的名称空间中被赋予一个唯一的名称，该名称空间被编码到相关的机器操作码中。这些名称用于引用数据对象。处理器可以可选地包括数据高速缓存，并且可以在单处理器或多任务环境中使用。对与别名寄存器条目相关联的存储器位置地址的引用将被重定向到中间存储器。

6. 发明授权

US07539602B2 Accelerating simulation of differential equation systems having continuous behavior 有权
标题翻译：加速具有连续行为的微分方程组的仿真
公开(公告)号：US07539602B2
公开(公告)日：2009-05-26
申请号：US11328629
申请日：2006-01-10
申请人： John Christopher Willis
发明人： John Christopher Willis
IPC分类号： G06F7/60 , G06F7/38
CPC分类号： G06F17/5036
摘要： An innovative method is taught for accelerating the simulation rate of differential equation systems having behavior piece-wise continuous in both value and time. Specifically, a system of differential equations representing the behavior of a physical system comprised of electronic, optical, or mechanical components may be simulated more rapidly using this method. The method utilizes incremental and iterative reconfiguration of digital logic wherein each configuration of the logic operates to yield a unique future value or range of values for each time-varying state variable within a system of equations representing a linear approximation of the original differential equation system for state variable values defined initially or at the onset of an iteration. Various configurations of the digital logic may be pre-computed or computed on demand, optionally caching such configurations for subsequent reuse.
摘要翻译：教授了一种创新的方法来加速具有在时间和时间上分段连续的行为的微分方程系统的模拟速率。具体地，可以使用该方法更快速地模拟表示由电子，光学或机械部件组成的物理系统的行为的微分方程系统。该方法利用数字逻辑的增量和迭代重新配置，其中逻辑的每个配置运行以产生表示系统内的每个时变状态变量的唯一的未来值或值的范围，其表示原始微分方程系统的线性近似，初始定义或迭代开始时定义的状态变量值。可以根据需要预先计算或计算数字逻辑的各种配置，任选地高速缓存这样的配置以供随后的重用。

7. 发明授权

US06223208B1 Moving data in and out of processor units using idle register/storage functional units 失效
标题翻译：使用空闲寄存器/存储功能单元将数据移入和移出处理器单元
公开(公告)号：US06223208B1
公开(公告)日：2001-04-24
申请号：US08943260
申请日：1997-10-03
申请人： Kenneth J. Kiefer , David A. Luick , John Christopher Willis
发明人： Kenneth J. Kiefer , David A. Luick , John Christopher Willis
IPC分类号： G06F900
CPC分类号： G06F9/3009 , G06F9/30123 , G06F9/3851 , G06F9/462
摘要： In a computer system and a processor which has the capability to do multithreaded processor, the computer system and processor use idle register/storage functional units within the processor core to transfer the state of a thread out of the processor to memory or from memory to the processor core. The register/storage functional units are interrogated dynamically so that this transfer occurs only when the register/storage functional units are idle and not being used for normal instructions. Thus, a state may be transferred in whole if there are many cycles when the register/storage functional unit is idle or it may be transferred in part if there an insufficient number of no-op instructions for the entire state. A context switch unit in the processor then has appropriate registers and logic control to keep track of the state of the thread that is being “idly” transferred and then transfer the remaining registers when a register/storage functional is available or “idle.”
摘要翻译：在具有执行多线程处理器能力的计算机系统和处理器中，计算机系统和处理器使用处理器核心内的空闲寄存器/存储功能单元将线程的状态从处理器传送到存储器或从存储器传输到存储器处理器核心。寄存器/存储功能单元被动态询问，以便仅当寄存器/存储功能单元空闲并且不用于正常指令时才发生该转移。因此，如果在寄存器/存储功能单元空闲时存在多个周期，或者如果整个状态的无操作指令数量不足，则状态可以全部传送。然后，处理器中的上下文切换单元具有适当的寄存器和逻辑控制，以跟踪正在“空转”的线程的状态，然后当寄存器/存储功能可用或“空闲”时传送剩余的寄存器。

8. 发明授权

US6088768A Method and system for maintaining cache coherence in a multiprocessor-multicache environment having unordered communication 失效
标题翻译：在具有无序通信的多处理器 - 多层次环境中保持高速缓存一致性的方法和系统
公开(公告)号：US6088768A
公开(公告)日：2000-07-11
申请号：US174648
申请日：1993-12-28
申请人： Donald Francis Baldus , Nancy Joan Duffield , Russell Dean Hoover , John Christopher Willis , Frederick Jacob Ziegler
发明人： Donald Francis Baldus , Nancy Joan Duffield , Russell Dean Hoover , John Christopher Willis , Frederick Jacob Ziegler
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0815 , G06F12/0813
摘要： A method and system for providing cache coherence despite unordered interconnect transport. In a computer system of multiple memory devices or memory units having shared memory and an interconnect characterized by unordered transport, the method comprises sending a request packet over the interconnect from a first memory device to a second memory device requiring that an action be carried out on shared memory held by the second memory device. If the second memory device determines that the shared memory is in a transient state, the second memory device returns the request packet to the first memory device; otherwise, the request is carried out by the second memory device. The first memory device will continue to resend the request packet each time that the request packet is returned.
摘要翻译：尽管无序互连传输，仍然提供高速缓存一致性的方法和系统。在具有共享存储器和由无序传输表征的互连的多个存储器设备或存储器单元的计算机系统中，该方法包括通过互连从第一存储器设备向第二存储器件发送请求包，要求执行操作由第二存储器件保持的共享存储器。如果第二存储装置确定共享存储器处于暂态状态，则第二存储装置将请求包返回给第一存储装置; 否则，请求由第二存储装置执行。每次返回请求包时，第一个存储设备将继续重新发送请求包。

9. 发明授权

US5999734A Compiler-oriented apparatus for parallel compilation, simulation and execution of computer programs and hardware models 失效
标题翻译：用于并行编译，仿真和执行计算机程序和硬件模型的面向编译器的设备
公开(公告)号：US5999734A
公开(公告)日：1999-12-07
申请号：US954843
申请日：1997-10-21
申请人： John Christopher Willis , Robert Neill Newshutz
发明人： John Christopher Willis , Robert Neill Newshutz
IPC分类号： G06F11/28 , G06F9/26 , G06F9/38 , G06F9/44 , G06F9/45 , G06F9/50 , G06F15/78 , G06F17/50
CPC分类号： G06F9/3877 , G06F15/7867 , G06F17/5009 , G06F17/5027 , G06F8/10 , G06F8/30 , G06F9/3897 , G06F2217/86
摘要： A distributed, compiler-oriented database is disclosed with operating modes including parallel compilation, parallel simulation and parallel execution of computer programs and hardware models. The invention utilizes a hardware apparatus consisting of shared memory multiprocessors, optionally augmented by processors with re-configurable logic execution pipelines or independently scheduled re-configurable logic blocks and a software database apparatus, manifest in the hardware apparatus, in order to efficiently support parallel database clients such as a source code analyzer, an elaborator, an optimizer, mapping and scheduling, code generation, linking/loading, execution/simulation, debugging, profiling, user interface and a file interface.
摘要翻译：公开了一种分布式，面向编译器的数据库，其操作模式包括并行编译，并行仿真和计算机程序和硬件模型的并行执行。本发明利用由共享存储器多处理器组成的硬件设备，可选地由具有可配置逻辑执行管线或独立调度的可重配置逻辑块的处理器和在硬件设备中显示的软件数据库设备增强，以便有效地支持并行数据库诸如源代码分析器，精简器，优化器，映射和调度，代码生成，链接/加载，执行/仿真，调试，分析，用户界面和文件接口等客户端。

10. 发明授权

US07328195B2 Semi-automatic generation of behavior models continuous value using iterative probing of a device or existing component model 有权
标题翻译：半自动生成行为模型连续值使用设备或现有组件模型的迭代探测
公开(公告)号：US07328195B2
公开(公告)日：2008-02-05
申请号：US10301173
申请日：2002-11-20
申请人： John Christopher Willis
发明人： John Christopher Willis
IPC分类号： G06N5/00
CPC分类号： G06F17/5036
摘要： A method is taught for increasing the steady-state verification speed of analog and mixed signal design through increased simulation speed, model abstraction by probing an existing component model or actual device and formal comparison of distinct component models.The innovative method taught here incrementally generates processor instructions optimized for operating the analog solver around a specific set of values (the operating context), caches sequences and applies the currently applicable operating context at each point in the simulation.The invention discloses a method for semi-automatically generating a mixed-signal or analog model based on iterative probing of an existing device or behavioral simulation.The invention teaches a method for model abstraction to alter the level of detail present in a running simulation. A means for graphically evaluating the match quality constitutes the final innovative step.The innovative method for the formal comparison of two analog or mixed signal models within a prescribed operating range for each interface between the model and its environment without the need for exhaustive simulation.
摘要翻译：通过提高模拟速度，通过探测现有组件模型或实际设备的模型抽象以及不同组件模型的形式比较，教授了一种提高模拟和混合信号设计的稳态验证速度的方法。这里教授的创新方法逐渐生成针对围绕特定值（操作上下文）操作模拟求解器而优化的处理器指令，缓存序列，并在模拟中的每个点应用当前适用的操作上下文。本发明公开了一种基于现有设备或行为模拟的迭代探测半自动生成混合信号或模拟模型的方法。本发明教导了一种用于模型抽象以改变运行模拟中存在的细节水平的方法。用于图形评估匹配质量的方法构成了最终的创新步骤。在模型和其环境之间的每个接口的规定工作范围内对两个模拟或混合信号模型进行正式比较的创新方法，而不需要详尽的模拟。

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