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1. 发明授权

US07120783B2 System and method for reading and writing a thread state in a multithreaded central processing unit 有权
公开(公告)号：US07120783B2
公开(公告)日：2006-10-10
申请号：US09888296
申请日：2001-06-22
申请人： David A. Fotland , Tibet Mimaroglu
发明人： David A. Fotland , Tibet Mimaroglu
IPC分类号： G06F9/34
CPC分类号： G06F9/3851 , G06F1/324 , G06F1/3275 , G06F9/3861 , G06F9/461 , G06F9/4881 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/24
摘要： A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.

2. 发明授权

US07047396B1 Fixed length memory to memory arithmetic and architecture for a communications embedded processor system 有权
标题翻译：用于通信嵌入式处理器系统的固定长度存储器到存储器算术和架构
公开(公告)号：US07047396B1
公开(公告)日：2006-05-16
申请号：US09888295
申请日：2001-06-22
申请人： David A. Fotland , Roger D. Arnold , Tibet Mimaroglu
发明人： David A. Fotland , Roger D. Arnold , Tibet Mimaroglu
IPC分类号： G06F7/38
CPC分类号： G06F9/3016 , G06F7/49994 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30167 , G06F9/30192 , G06F9/34 , G06F9/3812
摘要： A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, but the memory operand is variable in size. The size of the memory operand is specified by the instruction. Instructions in accordance with the present invention allow for multiple memory operands in a single fixed-length instruction. The instruction set is small and simple, so the implementation is lower cost than traditional processors. More addressing modes are provided for, thus creating a more efficient code. Semaphores are implemented using a single bit. Shift-and-merge instructions are used to access data across word boundaries.
摘要翻译：一种固定长度存储器到存储器处理固定长度指令的方法和系统。此外，本发明是用于实现与ALU宽度无关的存储器操作数宽度的方法和系统。算术和寄存器数据是32位，但存储器操作数的大小是可变的。存储器操作数的大小由指令指定。根据本发明的指令允许在单个固定长度指令中的多个存储器操作数。指令集小而简单，所以执行成本比传统处理器低。提供了更多的寻址模式，从而创建了更有效的代码。信号量使用单个位实现。移位和合并指令用于访问跨越边界的数据。

3. 发明授权

US06408380B1 Execution of an instruction to load two independently selected registers in a single cycle 有权
标题翻译：执行在一个周期内加载两个独立选择的寄存器的指令
公开(公告)号：US06408380B1
公开(公告)日：2002-06-18
申请号：US09316446
申请日：1999-05-21
申请人： Jerome C. Huck , Glenn T. Colon-Bonet , Alan H. Karp , David A. Fotland , Dean A. Mulla
发明人： Jerome C. Huck , Glenn T. Colon-Bonet , Alan H. Karp , David A. Fotland , Dean A. Mulla
IPC分类号： G06F9312
CPC分类号： G06F9/30043 , G06F9/30098 , G06F9/384
摘要： Method and apparatus for storing and executing an instruction to load two independent registers with two values is disclosed. In one embodiment, a computer-readable medium is encoded with an instruction including an opcode field specifying that the instruction is an instruction to load two independent registers with a first value and a second value, a source field specifying the first value and the second value, a first target register field specifying a first target register to load with the first value; a second target register field specifying a second target register to load with the second value. A system to execute the instruction is also disclosed.
摘要翻译：公开了用于存储和执行用于加载具有两个值的两个独立寄存器的指令的方法和装置。在一个实施例中，计算机可读介质用包括指定该指令是用于加载具有第一值和第二值的两个独立寄存器的指令的指令进行编码，指定第一值和第二值的源字段指定第一目标寄存器以第一值加载的第一目标寄存器字段; 指定第二目标寄存器的第二目标寄存器字段，以加载第二值。还公开了执行该指令的系统。

4. 发明授权

US4873627A Method and means for conditional storing of data in a reduced instruction set computer 失效
标题翻译：用于在精简指令集计算机中有条件地存储数据的方法和装置
公开(公告)号：US4873627A
公开(公告)日：1989-10-10
申请号：US139508
申请日：1987-12-30
申请人： Allen J. Baum , Terrence C. Miller , David A. Fotland
发明人： Allen J. Baum , Terrence C. Miller , David A. Fotland
IPC分类号： G06F9/22 , G06F9/30 , G06F9/305 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30072 , G06F9/30021
摘要： In a computer device in accordance with the preferred embodiment of the invention, an instruction set which uses a two-instruction sequence to store the result of a comparison is provided. The two-instruction sequence, which uses no branch instructions, does not need to wait for condition resolution before storing conditional results. Additionally, it also is capable of implementing slightly more general operations than simply storing a zero or one value of a comparison. Basically, the instruction set in accordance with the invention compares two operands and unconditionally stores a zero, which represents a Boolean "false", into a selected destination. The instruction set then conditionally nullifies the instruction following it, thus effecting a highly efficient execution of a sequence of instructions compared to the prior art.
摘要翻译：在根据本发明的优选实施例的计算机设备中，提供了使用两指令序列来存储比较结果的指令集。不使用分支指令的两个指令序列在存储条件结果之前不需要等待条件解析。另外，它也可以比简单地存储比较的零或一个值来实现稍微更一般的操作。基本上，根据本发明的指令集比较两个操作数，并且无条件地将一个表示布尔“假”的零存储到所选择的目的地中。然后，指令集有条件地使其后的指令无效，从而与现有技术相比，执行指令序列的高效执行。

5. 发明授权

US4747046A Mechanism for comparing two registers and storing the result in a general purpose register without requiring a branch 失效
标题翻译：用于比较两个寄存器并将结果存储在通用寄存器中而不需要分支的机制
公开(公告)号：US4747046A
公开(公告)日：1988-05-24
申请号：US750809
申请日：1985-06-28
申请人： Allen J. Baum , Terrence C. Miller , David A. Fotland
发明人： Allen J. Baum , Terrence C. Miller , David A. Fotland
IPC分类号： G06F9/22 , G06F9/30 , G06F9/305 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30072 , G06F9/30021
摘要： In a computer device, an instruction set which uses a two-instruction sequence to store the result of a comparison is provided. The two-instruction sequence, which uses no branch instructions, does not need to wait for condition resolution before storing conditional results. Additionally, it also is capable of implementing slightly more general operations than simply storing a zero or one value of a comparison. Basically, the instruction set in accordance with the invention compares two operands and unconditionally stores a zero, which represents a Boolean "false", into a selected destination. The instruction set then conditionally nullifies the instruction following it, thus effecting a highly efficient execution of a sequence of instructions compared to the prior art.
摘要翻译：在计算机装置中，提供了使用两指令序列来存储比较结果的指令集。不使用分支指令的两个指令序列在存储条件结果之前不需要等待条件解析。另外，它也可以比简单地存储比较的零或一个值来实现稍微更一般的操作。基本上，根据本发明的指令集比较两个操作数，并且无条件地将一个表示布尔“假”的零存储到所选择的目的地中。然后，指令集有条件地使其后的指令无效，从而与现有技术相比，执行指令序列的高效执行。

6. 发明授权

US5987576A Method and apparatus for generating and distributing clock signals with minimal skew 失效
标题翻译：用于以最小歪斜产生和分配时钟信号的方法和装置
公开(公告)号：US5987576A
公开(公告)日：1999-11-16
申请号：US807161
申请日：1997-02-27
申请人： Leith L. Johnson , David A. Fotland
发明人： Leith L. Johnson , David A. Fotland
IPC分类号： G11C11/407 , G06F1/10 , G06F12/00 , G11C7/00 , G11C7/22 , G11C11/401 , G06F1/00
CPC分类号： G11C7/22
摘要： A memory controller and at least one memory module exchange data at high transfer rates by minimizing clock skew. When writing data to the memory module, the memory controller generates a clock signal that travels along a first clock line segment. The data bus carries the write data, and the electrical characteristics of the data bus and first clock line segment are matched such that incident wavefronts of the data bus and clock signal arrive at the memory module in fixed relation to one another. When reading data, the first clock line segment is looped back from the memory module to the memory controller along a second clock line segment, with a copy of the clock signal provided on the second clock line segment. The data bus carries the read data, and the electrical characteristics of the data bus and the first clock line segment are matched such that incident wavefronts of the data bus and clock signal arrive at the memory controller in fixed relationship to one another. The present invention provides a substantial increase in memory bandwidth with minimal design changes to prior art memory systems.
摘要翻译：存储器控制器和至少一个存储器模块通过最小化时钟偏移来以高传输速率交换数据。当将数据写入存储器模块时，存储器控制器产生沿着第一时钟线段行进的时钟信号。数据总线携带写数据，数据总线和第一时钟线段的电气特性相匹配，使得数据总线和时钟信号的入射波前相互固定地连接到存储器模块。当读取数据时，第一时钟线段沿着第二时钟线段从存储器模块循环回存储器控制器，并且在第二时钟线段上提供时钟信号的副本。数据总线携带读取数据，数据总线和第一时钟线段的电气特性相匹配，使得数据总线和时钟信号的入射波前相互固定地连接到存储器控制器。本发明通过对现有技术存储器系统的最小设计改变来提供存储器带宽的显着增加。

7. 发明授权

US07308686B1 Software input/output using hard real time threads 有权
标题翻译：使用硬实时线程的软件输入/输出
公开(公告)号：US07308686B1
公开(公告)日：2007-12-11
申请号：US10360128
申请日：2003-02-07
申请人： David A. Fotland , Nicholas J. Kelsey
发明人： David A. Fotland , Nicholas J. Kelsey
IPC分类号： G06F9/46 , G06F1/04 , G06F7/38
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/461
摘要： A system and method for implementing high speed input and output protocols in software using hard real time threads. The processor provides both high speed and deterministic performance. The hard real time threads execute enough instructions per clock cycle of the input and output protocol to regularly transfer data.
摘要翻译：一种使用硬实时线程在软件中实现高速输入和输出协议的系统和方法。处理器提供高速和确定性的性能。硬实时线程在输入和输出协议的每个时钟周期执行足够的指令以定期传输数据。

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