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1. 发明授权

US6140236A High throughput A1-Cu thin film sputtering process on small contact via for manufacturable beol wiring 失效
标题翻译：用于制造蜂窝布线的小接触通孔的高通量A1-Cu薄膜溅射工艺
公开(公告)号：US6140236A
公开(公告)日：2000-10-31
申请号：US63094
申请日：1998-04-21
申请人： Darryl Restaino , Chi-Hua Yang , Hans W. Poetzlberger , Tomio Katata , Hideaki Aochi
发明人： Darryl Restaino , Chi-Hua Yang , Hans W. Poetzlberger , Tomio Katata , Hideaki Aochi
IPC分类号： H01L23/52 , C23C14/16 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： C23C14/165 , H01L21/2855 , H01L21/76877
摘要： A metal interconnect layer that fills in a via hole formed by first depositing a first Al--Cu film on the sidewalls of the via hole at a low temperature and a low sputtering power and then depositing a second Al--Cu film on the first Al--Cu film at a high temperature and high sputtering power. Sputtering is performed in two steps at low and high temperatures within the same sputtering chamber. The deposition at low temperature and low sputtering power provides good coverage in the via hole, and the deposition at high temperature and high sputtering power reduces the process time.
摘要翻译：一种金属互连层，其填充通过在低温和低溅射功率下首先在通孔的侧壁上沉积第一Al-Cu膜形成的通孔，然后在第一Al-Cu膜上沉积第二Al-Cu膜， Cu膜在高温和高溅射功率下。溅射在相同溅射室内的低温和高温下分两步进行。在低温和低溅射功率下的沉积在通孔中提供了良好的覆盖，并且在高温和高溅射功率下的沉积减少了处理时间。

2. 发明申请

US20060189153A1 Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same 有权
公开(公告)号：US20060189153A1
公开(公告)日：2006-08-24
申请号：US11406595
申请日：2006-04-19
申请人： Daniel Edelstein , Alfred Grill , Vishnubhai Patel , Darryl Restaino
发明人： Daniel Edelstein , Alfred Grill , Vishnubhai Patel , Darryl Restaino
IPC分类号： H01L23/58 , H01L21/31
CPC分类号： H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02274 , H01L21/02315 , H01L21/3122 , H01L21/31633 , H01L21/76826 , H01L21/76832 , H01L21/76834
摘要： A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.

3. 发明申请

US20060134911A1 MANUFACTURABLE CoWP METAL CAP PROCESS FOR COPPER INTERCONNECTS 有权
标题翻译：铜制互连的可制造CoWP金属封盖工艺
公开(公告)号：US20060134911A1
公开(公告)日：2006-06-22
申请号：US10905230
申请日：2004-12-22
申请人： Darryl Restaino , Donald Canaperi , Judith Rubino , Sean Smith , Richard Henry , James Fluegel , Mahadevaiyer Krishnan
发明人： Darryl Restaino , Donald Canaperi , Judith Rubino , Sean Smith , Richard Henry , James Fluegel , Mahadevaiyer Krishnan
IPC分类号： H01L21/44
CPC分类号： H01L21/288 , C23C18/1241 , C23C18/1607 , C23C18/1608 , C23C18/1844 , C23C18/50 , H01L21/76849 , H01L21/76874 , H05K3/244 , H05K2203/0716 , H05K2203/072
摘要： A method to electrolessly plate a CoWP alloy on copper in a reproducible manner that is effective for a manufacturable process. In the method, a seed layer of palladium (Pd) is deposited on the copper by an aqueous seeding solution of palladium acetate, acetic acid and chloride. Thereafter, a complexing solution is applied to remove any Pd ions which are adsorbed on surfaces other than the copper. Finally, a plating solution of cobalt (Co), tungsten (W) and phosphorous (P) is applied to the copper so as to deposit a layer of CoWP on the Pd seed and copper.
摘要翻译：一种以可再生的方式对铜上的CoWP合金进行无电镀的方法，该方法对于可制造的工艺是有效的。在该方法中，通过乙酸钯，乙酸和氯化物的水性接种溶液将铜（Pd）种子层沉积在铜上。此后，应用络合溶液以除去吸附在除铜之外的表面上的任何Pd离子。最后，将铜（Co），钨（W）和磷（P）的电镀溶液施加到铜上，以便在Pd种子和铜上沉积CoWP层。

4. 发明授权

US06806182B2 Method for eliminating via resistance shift in organic ILD 失效
标题翻译：消除有机ILD中电阻移位的方法
公开(公告)号：US06806182B2
公开(公告)日：2004-10-19
申请号：US10137274
申请日：2002-05-01
申请人： Darryl Restaino , Shahab Siddiqui , Erdem Kaltalioglu , Delores Bennett , Chih-Chih Liu , Hsueh-Chung Chen , Tong-Yu Chen , Gwo-Shii Yang , Chiung-Sheng Hsiung
发明人： Darryl Restaino , Shahab Siddiqui , Erdem Kaltalioglu , Delores Bennett , Chih-Chih Liu , Hsueh-Chung Chen , Tong-Yu Chen , Gwo-Shii Yang , Chiung-Sheng Hsiung
IPC分类号： H01L214763
CPC分类号： H01L21/02252 , H01L21/02118 , H01L21/02164 , H01L21/022 , H01L21/02203 , H01L21/02304 , H01L21/02323 , H01L21/0234 , H01L21/3121 , H01L21/31695 , H01L21/76826 , H01L21/76832 , H01L21/76834
摘要： Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.
摘要翻译：在覆盖有机层间介质之前，将粘合促进剂施加到覆盖层和粘附促进剂的氧化之后，减少了体现多层金属和有机层间电介质的半导体晶片的热循环过程中的电阻问题。

5. 发明申请

US20070190804A1 Minimizing low-k dielectric damage during plasma processing 有权
标题翻译：最小化等离子体处理过程中的低k电介质损伤
公开(公告)号：US20070190804A1
公开(公告)日：2007-08-16
申请号：US11352047
申请日：2006-02-10
申请人： Michael Beck , John Fitzsimmons , Karl Hornik , Darryl Restaino
发明人： Michael Beck , John Fitzsimmons , Karl Hornik , Darryl Restaino
IPC分类号： H01L21/31
CPC分类号： H01L21/3105 , H01L21/02074 , H01L21/31058 , H01L21/76814 , H01L21/76826 , H01L21/76834
摘要： Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (≦2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.
摘要翻译：本发明的实施例提供一种具有介电材料的半导体器件及其制造方法。一种方法包括ILD表面的短（<= 2秒）闪光激活，随后在活化的ILD表面上流动诸如硅烷DEMS之类的前体。前体与活化的ILD表面反应，从而有选择地保护ILD表面。受保护的ILD表面耐等离子体处理损伤。受保护的ILD表面消除了使用硬掩模保护电介质免受等离子体损伤的要求。

6. 发明申请

US20060183345A1 ADVANCED LOW DIELECTRIC CONSTANT ORGANOSILICON PLASMA CHEMICAL VAPOR DEPOSITION FILMS 有权
标题翻译：高级低介电常数有机硅等离子体化学气相沉积膜
公开(公告)号：US20060183345A1
公开(公告)日：2006-08-17
申请号：US10906370
申请日：2005-02-16
申请人： Son Nguyen , Sarah Lane , Jia Lee , Kensaku Ida , Darryl Restaino , Takeshi Nogami
发明人： Son Nguyen , Sarah Lane , Jia Lee , Kensaku Ida , Darryl Restaino , Takeshi Nogami
IPC分类号： H01L21/31
CPC分类号： H01L21/7682 , C23C16/401 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02354 , H01L21/3122 , H01L21/31633 , H01L2221/1047
摘要： A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.
摘要翻译：在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高键合相互作用，提供比现有技术的SiCOH电介质更多的碳作为甲基端基和较少的亚甲基-CH 2 - 2交联基团。 SiCOH电介质的特征在于具有包含小于约1.40的CH 3 N 2 CH 2拉伸的峰面积的FTIR光谱，SiH拉伸的峰面积小于约0.20，SiCH 3键的峰面积大于约2.0，Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％。

7. 发明授权

US5641992A Metal interconnect structure for an integrated circuit with improved electromigration reliability 失效
标题翻译：具有改善的电迁移可靠性的集成电路的金属互连结构
公开(公告)号：US5641992A
公开(公告)日：1997-06-24
申请号：US513494
申请日：1995-08-10
申请人： Pei-Ing Paul Lee , Bernd Vollmer , Darryl Restaino , Bill Klaasen
发明人： Pei-Ing Paul Lee , Bernd Vollmer , Darryl Restaino , Bill Klaasen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76843 , H01L21/28512 , H01L21/7685 , H01L21/76877 , H01L23/53223 , H01L2924/0002
摘要： A multilayer interconnect structure for a semiconductor integrated circuit comprising a base layer of titanium, a second layer of titanium nitride, a third layer of an aluminum alloy and a top layer of titanium nitride. All of the layers contained within the multilayer interconnect structure are deposited by in-situ deposition in an ultra-high vacuum deposition system. The different layers deposited in the deposition system are conducted consecutively without a disruption to the vacuum. Although each layer in the multilayer interconnect structure are deposited within the integrated ultra-high vacuum deposition system, with multiple deposition chambers, the deposition of the different layers is conducted at different temperatures. The time to the electromigration failure of the multilayer interconnect structure, caused by the electromigration of the aluminum alloy, is greatly increased by depositing the aluminum alloy layer at a temperature in excess of 300.degree. C. and preferably between 350.degree. C. and 550.degree. C. The titanium layer and the adjacent titanium nitride layer below the aluminum alloy layer provide the interconnect structure with low resistivity and prevent alloy spiking of the base substrate. As a result, a multilayer interconnect structure provided that has improved electromigration reliability and a low resistance, thereby enabling more dense applications within an integrated circuit.
摘要翻译：一种用于半导体集成电路的多层互连结构，包括钛基底层，第二氮化钛层，第三层铝合金和顶层氮化钛。包含在多层互连结构内的所有层通过原位沉积沉积在超高真空沉积系统中。沉积在沉积系统中的不同层连续进行，而不会破坏真空。尽管多层互连结构中的每个层都沉积在具有多个沉积室的集成超高真空沉积系统内，但不同层的沉积在不同的温度下进行。通过在超过300℃，优选350℃至550℃的温度下沉积铝合金层，由铝合金的电迁移引起的多层互连结构的电迁移故障的时间大大增加。 C.在铝合金层下面的钛层和相邻的氮化钛层提供具有低电阻率的互连结构并防止基底衬底的合金尖峰。结果，提供了具有改善的电迁移可靠性和低电阻的多层互连结构，从而使集成电路内的应用更加密集。

8. 发明授权

US07691736B2 Minimizing low-k dielectric damage during plasma processing 有权
标题翻译：最小化等离子体处理过程中的低k电介质损伤
公开(公告)号：US07691736B2
公开(公告)日：2010-04-06
申请号：US11352047
申请日：2006-02-10
申请人： Michael Beck , John A. Fitzsimmons , Karl Hornik , Darryl Restaino
发明人： Michael Beck , John A. Fitzsimmons , Karl Hornik , Darryl Restaino
IPC分类号： H01L21/4763
CPC分类号： H01L21/3105 , H01L21/02074 , H01L21/31058 , H01L21/76814 , H01L21/76826 , H01L21/76834
摘要： Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (≦2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.
摘要翻译：本发明的实施例提供一种具有介电材料的半导体器件及其制造方法。一种方法包括ILD表面的短（＆nlE; 2秒）闪光激活，随后在活化的ILD表面上流动诸如硅烷DEMS之类的前体。前体与活化的ILD表面反应，从而有选择地保护ILD表面。受保护的ILD表面耐等离子体处理损伤。受保护的ILD表面消除了使用硬掩模来保护电介质免受等离子体损伤的要求。

9. 发明申请

US20070215842A1 MANUFACTURABLE CoWP METAL CAP PROCESS FOR COPPER INTERCONNECTS 有权
标题翻译：铜制互连的可制造CoWP金属封盖工艺
公开(公告)号：US20070215842A1
公开(公告)日：2007-09-20
申请号：US11751788
申请日：2007-05-22
申请人： Darryl Restaino , Donald Canaperi , Judith Rubino , Sean Smith , Richard Henry , James Fluegel , Mahadevaiyer Krishnan
发明人： Darryl Restaino , Donald Canaperi , Judith Rubino , Sean Smith , Richard Henry , James Fluegel , Mahadevaiyer Krishnan
IPC分类号： H01B1/02
CPC分类号： H01L21/288 , C23C18/1241 , C23C18/1607 , C23C18/1608 , C23C18/1844 , C23C18/50 , H01L21/76849 , H01L21/76874 , H05K3/244 , H05K2203/0716 , H05K2203/072
摘要： An aqueous seeding solution of palladium acetate, acetic acid and chloride.
摘要翻译：乙酸钯，乙酸和氯化钠的水溶液接种溶液。

10. 发明申请

US20070128882A1 ADVANCED LOW DIELECTRIC CONSTANT ORGANOSILICON PLASMA CHEMICAL VAPOR DEPOSITION FILMS 有权
标题翻译：高级低介电常数有机硅等离子体化学气相沉积膜
公开(公告)号：US20070128882A1
公开(公告)日：2007-06-07
申请号：US11671022
申请日：2007-02-05
申请人： Son Nguyen , Sarah Lane , Jia Lee , Kensaku Ida , Darryl Restaino , Takeshi Nogami
发明人： Son Nguyen , Sarah Lane , Jia Lee , Kensaku Ida , Darryl Restaino , Takeshi Nogami
IPC分类号： H01L21/31
CPC分类号： H01L21/7682 , C23C16/401 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02354 , H01L21/3122 , H01L21/31633 , H01L2221/1047
摘要： A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.
摘要翻译：在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高键合相互作用，提供比现有技术的SiCOH电介质更多的碳作为甲基端基和较少的亚甲基-CH 2 - 2交联基团。 SiCOH电介质的特征在于具有小于约1.40的CH 3/3 CH 2拉伸的峰面积的FTIR光谱，SiH拉伸的峰面积小于约0.20，SiCH 3键的峰面积大于约2.0，Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％。

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