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1. 发明授权

US07089136B2 Method for reduced electrical fusing time 失效
标题翻译：降低电熔时间的方法
公开(公告)号：US07089136B2
公开(公告)日：2006-08-08
申请号：US10604414
申请日：2003-07-18
申请人： Darren L. Anand , John E. Barth, Jr. , Steven F. Oakland , Michael R. Ouellette
发明人： Darren L. Anand , John E. Barth, Jr. , Steven F. Oakland , Michael R. Ouellette
IPC分类号： G01R31/00
CPC分类号： G11C17/16 , G11C17/18
摘要： An electrical fuse circuit design for reducing the testing time for a semiconductor device manufactured with redundant eFuse circuitry. A two-to-one multiplexer (MUX) is provided at each eFuse circuit in addition to the fuse latch and pattern latch. Information on which fuse is to be blown is stored in the fuse's pattern latch. The output of the pattern latch is ANDed with a program input to provide a select signal for the MUX. Based on the select signal, the MUX allows the shifted “1” to either go to the next latch in the shift chain or bypass the next latch or latches in the shift chain when the next fuse(s) is not to be blown. Accordingly, the invention enables only those fuse latches associated with fuses that are to be blown to hold up the propagation of the shifted “1” to the next eFuse circuits.
摘要翻译：一种电熔丝回路设计，用于减少用冗余eFuse电路制造的半导体器件的测试时间。除了熔丝锁存器和图案锁存器之外，每个eFuse电路还提供一对二路复用器（MUX）。保险丝图案锁存器中存储有要熔断保险丝的信息。模式锁存器的输出与程序输入进行“与”运算以提供MUX的选择信号。基于选择信号，MUX允许移位的“1”进入移位链中的下一个锁存器，或者在下一个保险丝不被熔断时，旁路下一个锁存器或锁存在换档链中。因此，本发明仅能够使与熔断器相关联的熔丝锁存器保持被转换的“1”传播到下一个eFuse电路。

2. 发明授权

US07243279B2 Method for separating shift and scan paths on scan-only, single port LSSD latches 失效
标题翻译：用于在仅扫描单端口LSSD锁存器上分离移位和扫描路径的方法
公开(公告)号：US07243279B2
公开(公告)日：2007-07-10
申请号：US10604908
申请日：2003-08-26
申请人： Darren L. Anand , John E. Barth, Jr. , Steven F. Oakland , Michael R. Ouellette
发明人： Darren L. Anand , John E. Barth, Jr. , Steven F. Oakland , Michael R. Ouellette
IPC分类号： G01R31/28
CPC分类号： G01R31/318536 , G01R31/318544
摘要： A method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only, without increasing the device's internal real estate and without substantial increase in overall device real estate. The circuit design eliminates the need for additional logic components to be built into the internal circuitry of the device and also eliminates the cost of providing dual port LSSD latches within the device. Implementation of the invention involves providing a unique configuration of low level logic components as input circuitry that is coupled to a pair of single port LSSD latches that operate as the input latches for the device. The low level logic components accomplishes the splitting of scan chain inputs and shift chain inputs to the input latches and thus enables the single ported LSSD latches to operate with similar functionality as dual ported LSSD latches.
摘要翻译：一种方法和电路设计，用于仅使用设计用于扫描路径功能的单端口LSSD锁存器实现移位路径和扫描路径功能，而不会增加设备的内部房地产，而且整体设备的不动产不会大幅增加。电路设计消除了对设备内部电路内置的其他逻辑元件的需求，并且消除了在器件内提供双端口LSSD锁存器的成本。本发明的实现涉及提供作为输入电路的低级逻辑组件的独特配置，该输入电路耦合到作为设备的输入锁存器操作的一对单端口LSSD锁存器。低电平逻辑组件完成扫描链输入和移位链输入到输入锁存器的分割，从而使单端口LSSD锁存器能够与双端口LSSD锁存器类似的功能运行。

3. 发明授权

US06995585B2 System and method for implementing self-timed decoded data paths in integrated circuits 有权
标题翻译：在集成电路中实现自定时解码数据路径的系统和方法
公开(公告)号：US06995585B2
公开(公告)日：2006-02-07
申请号：US10604621
申请日：2003-08-05
申请人： Darren L. Anand , John E. Barth, Jr.
发明人： Darren L. Anand , John E. Barth, Jr.
IPC分类号： H03K19/00
CPC分类号： H03K19/0008
摘要： A self-timed data transmission system includes a data bit group defined by at least two data bits to be transmitted from a corresponding plurality of transmitting storage elements. A corresponding plurality of data receiving storage elements receives the data transmitted from said transmitting storage elements. Encoding logic is used for encoding the transmitted data from the transmitting storage elements, wherein the encoded transmitted data is coupled to a plurality of data lines. The encoding logic is further configured so as to result in only one of the plurality of data lines being activated during a given data transmission cycle.
摘要翻译：自定时数据传输系统包括由相应的多个发送存储元件发送的至少两个数据位定义的数据位组。相应的多个数据接收存储元件接收从所述发送存储元件发送的数据。编码逻辑用于对来自发送存储元件的发送数据进行编码，其中编码的发送数据耦合到多条数据线。编码逻辑被进一步配置为使得在给定的数据传输周期期间只有多条数据线中的一条被激活。

4. 发明授权

US06788591B1 System and method for direct write to dynamic random access memory (DRAM) using PFET bit-switch 有权
标题翻译：使用PFET位开关直接写入动态随机存取存储器（DRAM）的系统和方法
公开(公告)号：US06788591B1
公开(公告)日：2004-09-07
申请号：US10604909
申请日：2003-08-26
申请人： Darren L. Anand , John E. Barth, Jr.
发明人： Darren L. Anand , John E. Barth, Jr.
IPC分类号： G11C700
CPC分类号： G11C7/1096 , G11C7/1078 , G11C11/4076 , G11C2207/002 , G11C2207/229
摘要： A control circuit for a memory array device having one or more memory storage cells associated therewith includes a true bit-line and a complementary bit-line coupled to the one or more memory storage cells. A sense amplifier is coupled to the true and complementary bit-lines, the sense amplifier being configured to amplify a small voltage difference between the true bit-line and the complementary bit-line to a full level signal at predetermined high and low logic voltage levels. A bit-switch pair selectively couples the bit-lines and said sense amplifier to fan-in circuitry, and is further configured so as to couple the fan-in circuitry to the true and complementary bit-lines prior to the activation of a wordline associated with a selected cell for a write operation thereto. Thereby, the write operation to the selected cell is commenced prior to the completion of time associated with signal development on the true and complementary bit-lines.
摘要翻译：用于具有与其相关联的一个或多个存储器单元的存储器阵列器件的控制电路包括耦合到该一个或多个存储单元的真位位线和互补位线。感测放大器耦合到真和互补的位线，读出放大器被配置为在预定的高和低逻辑电压电平下将真位位线和互补位线之间的小的电压差放大到全电平信号。位开关对将位线和所述读出放大器选择性地耦合到扇入电路，并且还被配置为在激活字线相关联之前将风扇进入电路耦合到真实和互补的位线与选择的单元进行写操作。因此，在完成与真实和互补位线上的信号开发相关联的时间之前，对所选单元的写操作开始。

5. 发明授权

US06552938B1 Column redundancy system and method for embedded DRAM devices with multibanking capability 有权
标题翻译：具有多网段能力的嵌入式DRAM器件的列冗余系统和方法
公开(公告)号：US06552938B1
公开(公告)日：2003-04-22
申请号：US09971840
申请日：2001-10-05
申请人： Darren L. Anand , John E. Barth, Jr.
发明人： Darren L. Anand , John E. Barth, Jr.
IPC分类号： G11C700
CPC分类号： G11C29/802 , G11C29/848 , G11C2207/104
摘要： A column redundancy system is disclosed for a memory array having a page structure organized into columns and data lines. In an exemplary embodiment of the invention, the system includes a steering logic network for coupling a memory input/output (I/O) device to the memory array. A storage register is in communication with the steering logic network, the storage register for storing location information for defective data lines in the memory array. During a memory operation, the location information stored in the storage register is transmitted to the steering logic network, the storage register further having the location information loaded therein prior to the memory operation. Thereby, the steering logic network prevents any of the defective data lines from being coupled to the I/O device.
摘要翻译：公开了一种具有组织成列和数据线的页面结构的存储器阵列的列冗余系统。在本发明的示例性实施例中，该系统包括用于将存储器输入/输出（I / O）设备耦合到存储器阵列的转向逻辑网络。存储寄存器与转向逻辑网络通信，存储寄存器用于存储存储器阵列中的有缺陷的数据线的位置信息。在存储器操作期间，将存储在存储寄存器中的位置信息发送到转向逻辑网络，在存储器操作之前，存储寄存器还具有加载其中的位置信息。因此，转向逻辑网络防止任何有缺陷的数据线耦合到I / O设备。

6. 发明授权

US06728159B2 Flexible multibanking interface for embedded memory applications 有权
标题翻译：嵌入式存储器应用的灵活多银行接口
公开(公告)号：US06728159B2
公开(公告)日：2004-04-27
申请号：US10026118
申请日：2001-12-21
申请人： Darren L. Anand , John E. Barth, Jr.
发明人： Darren L. Anand , John E. Barth, Jr.
IPC分类号： G11C800
CPC分类号： G11C7/1006 , G11C7/22 , G11C29/70 , G11C2207/104
摘要： A growable multibank DRAM macro is achieved with a flexible multibank interface which can be grown without redesign and without change of appearance/behavior to the customer. The interface is preferably characterized by the presence of bank select inputs (pins) which permit selection of one or more banks of the macro. The banks preferably each have respective row decode circuitry and respective limited repair redundancy.
摘要翻译：可扩展的多存储器DRAM宏可以通过灵活的多存储器接口来实现，可以在不重新设计的情况下生长，而不会改变客户的外观/行为。该接口的特征在于存在允许选择宏块的一个或多个存储体的存储体选择输入（引脚）。这些组优选地各自具有相应的行解码电路和相应的有限维修冗余。

7. 发明授权

US06766468B2 Memory BIST and repair 有权
标题翻译：记忆BIST和修复
公开(公告)号：US06766468B2
公开(公告)日：2004-07-20
申请号：US09682023
申请日：2001-07-11
申请人： John E. Barth, Jr. , Jeffrey H. Dreibelbis , Michael R. Ouellette
发明人： John E. Barth, Jr. , Jeffrey H. Dreibelbis , Michael R. Ouellette
IPC分类号： H02H305
CPC分类号： G11C29/44 , G11C29/72 , G11C2029/1208
摘要： A method of memory BIST (Built-In Self Test) and memory repair that stores a redundancy calculation on-chip, as opposed to scanning this data off-chip for later use. This method no longer requires level-sensitive scan design (LSSD) scanning of memory redundancy data off-chip to the tester, and therefore does not require re-contacting of the chip for electrical fuse blow.
摘要翻译：内存BIST（内置自检）和内存修复方法，用于存储片上冗余计算，而不是将数据片外扫描以备以后使用。该方法不再需要对测试仪进行片外存储器冗余数据的电平敏感扫描设计（LSSD）扫描，因此不需要再次接触芯片进行电熔丝熔断。

8. 发明授权

US08937345B2 Integrated circuits comprising an active transistor electrically connected to a trench capacitor by an overlying contact 有权
标题翻译：集成电路包括通过上覆触点与沟槽电容器电连接的有源晶体管
公开(公告)号：US08937345B2
公开(公告)日：2015-01-20
申请号：US13454635
申请日：2012-04-24
申请人： John E. Barth, Jr. , Kangguo Cheng , Michael Sperling , Geng Wang
发明人： John E. Barth, Jr. , Kangguo Cheng , Michael Sperling , Geng Wang
IPC分类号： H01L27/108 , H01L21/768 , H01L23/485
CPC分类号： H01L21/76895 , H01L23/485 , H01L27/10867 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.
摘要翻译：集成电路包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着所述沟槽电容器的外围设置以隔离所述沟槽电容器; 与有源晶体管横向隔开的无源晶体管，其中所述沟槽电容器的至少一部分插入在所述有源和无源晶体管之间; 布置在有源和无源晶体管上的层间电介质; 以及第一导电接触件，其延伸穿过所述有源晶体管的所述有源晶体管和所述沟槽电容器的所述至少一部分的所述层间电介质的漏极结到所述有源和无源晶体管之间，其中所述第一导电接触将所述沟槽电容器电连接到所述沟道电容器有源晶体管。

9. 发明授权

US08263472B2 Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices 失效
标题翻译：用于绝缘体上硅（SOI）器件的深沟槽静电放电（ESD）保护二极管
公开(公告)号：US08263472B2
公开(公告)日：2012-09-11
申请号：US13324486
申请日：2011-12-13
申请人： John E. Barth, Jr. , Kerry Bernstein
发明人： John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L21/76
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L23/535 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
摘要翻译：半导体包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层，第二极性类型的带区域直接设置在掩埋绝缘体层的正下方并形成导电路径，第二极性类型的阱区域布置在本体衬底中并与带区域接触，填充有导电材料的深沟槽设置在阱区内的第一极性类型和由深沟槽的下部与阱区之间的接合部限定的静电放电（ESD）保护二极管。

10. 发明授权

US08097525B2 Vertical through-silicon via for a semiconductor structure 有权
标题翻译：用于半导体结构的垂直通硅硅通孔
公开(公告)号：US08097525B2
公开(公告)日：2012-01-17
申请号：US12201580
申请日：2008-08-29
申请人： John E. Barth, Jr. , Kerry Bernstein
发明人： John E. Barth, Jr. , Kerry Bernstein
IPC分类号： H01L21/00
CPC分类号： H01L23/481 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.
摘要翻译：半导体结构包括具有第一和第二平面表面的至少一个硅衬底，以及填充有导电材料并且至少穿过至少一个硅衬底的第一平坦表面垂直延伸到其第二平坦表面的至少一个穿硅通孔。穿通硅通孔在多个电子电路之间形成垂直互连，并且围绕穿过硅通孔的绝缘绝缘体的量基于硅通孔的限定功能而变化。

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