专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080244108A1 PER-PORT UNIVERSAL SERIAL BUS DISABLE 审中-公开
标题翻译： PER-PORT通用串行总线禁用
公开(公告)号：US20080244108A1
公开(公告)日：2008-10-02
申请号：US11693569
申请日：2007-03-29
申请人： Darren L. Abramson , Jeffrey T. Brown , Robert W. Strong
发明人： Darren L. Abramson , Jeffrey T. Brown , Robert W. Strong
IPC分类号： G06F3/00
CPC分类号： G06F13/4291 , G06F21/85
摘要： A device and system are disclosed. In one embodiment, the device includes a register to store a universal serial bus (USB) port disable bit for an individual USB port. The device also includes a USB individual port disable unit that is capable of reading the USB port disable bit and disabling the individual USB port when the bit is set.
摘要翻译：公开了一种设备和系统。在一个实施例中，该设备包括用于存储用于各个USB端口的通用串行总线（USB）端口禁用位的寄存器。该设备还包括一个USB独立端口禁用单元，可以读取USB端口禁用位，并在该位置1时禁用各个USB端口。

2. 发明申请

US20130054856A1 Providing Adaptive Bandwidth Allocation For A Fixed Priority Arbiter 有权
标题翻译：为固定优先仲裁器提供自适应带宽分配
公开(公告)号：US20130054856A1
公开(公告)日：2013-02-28
申请号：US13222354
申请日：2011-08-31
申请人： Kie Woon Lim , E-Liang Chew , Khee Wooi Lee , Darren L. Abramson
发明人： Kie Woon Lim , E-Liang Chew , Khee Wooi Lee , Darren L. Abramson
IPC分类号： G06F13/14 , G06F1/04
CPC分类号： G06F13/14 , G06F13/364
摘要： In one embodiment, the present invention includes a method for receiving requests from requestors in an arbiter, detecting that none of the requestors have a qualified request for at least one cycle of an arbitration round, and preventing a grant count reload of grant counters associated with the when at least one of the requestors has available grants for the arbitration round. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在仲裁器中接收来自请求者的请求的方法，检测到所有请求者都不具有至少一个仲裁循环周期的合格请求，并且防止授权计数重新加载与当至少有一个请求者有可用的仲裁通知时。描述和要求保护其他实施例。

3. 发明授权

US08386682B2 Method, apparatus and system for maintaining transaction coherecy in a multiple data bus platform 有权
标题翻译：用于在多数据总线平台中维持交易同步的方法，装置和系统
公开(公告)号：US08386682B2
公开(公告)日：2013-02-26
申请号：US12827684
申请日：2010-06-30
申请人： Kah Meng Yeem , Mikal C. Hunsaker , Darren L. Abramson , Raul N. Gutierrez , Khee Wooi Lee
发明人： Kah Meng Yeem , Mikal C. Hunsaker , Darren L. Abramson , Raul N. Gutierrez , Khee Wooi Lee
IPC分类号： G06F13/36 , G06F12/00
CPC分类号： G06F13/4031 , G06F13/364
摘要： Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests—e.g. between those requestors providing the access requests—the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.
摘要翻译：在多总线计算机体系结构中保持交易顺序的技术。在一个实施例中，仲裁器从多个请求者接收访问请求，每个访问请求请求对总线的相应访问。基于访问请求之间的仲裁，例如在提供访问请求的那些请求者之间，仲裁器可以产生触发在第一总线上携带第一消息的授权消息。在某些实施例中，授权消息进一步触发在第二总线上的第一消息的另一个携带。

4. 发明申请

US20120005386A1 METHOD, APPARATUS AND SYSTEM FOR MAINTAINING TRANSACTION COHERECY IN A MULTIPLE DATA BUS PLATFORM 有权
标题翻译：在多个数据总线平台中维护交易共享的方法，装置和系统
公开(公告)号：US20120005386A1
公开(公告)日：2012-01-05
申请号：US12827684
申请日：2010-06-30
申请人： Kah Meng Yeem , Mikal C. Hunsaker , Darren L. Abramson , Raul N. Gutierrez , Khee Wooi Lee
发明人： Kah Meng Yeem , Mikal C. Hunsaker , Darren L. Abramson , Raul N. Gutierrez , Khee Wooi Lee
IPC分类号： G06F13/36
CPC分类号： G06F13/4031 , G06F13/364
摘要： Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests—e.g. between those requestors providing the access requests—the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.
摘要翻译：在多总线计算机体系结构中保持交易顺序的技术。在一个实施例中，仲裁器从多个请求者接收访问请求，每个访问请求请求对总线的相应访问。基于访问请求之间的仲裁，例如在提供访问请求的那些请求者之间，仲裁器可以产生触发在第一总线上携带第一消息的授权消息。在某些实施例中，授权消息进一步触发在第二总线上的第一消息的另一个携带。

5. 发明授权

US07990999B2 Starvation prevention scheme for a fixed priority PCE-express arbiter with grant counters using arbitration pools 有权
标题翻译：使用仲裁池的固定优先级PCE-express仲裁器与授权计数器的饥饿预防方案
公开(公告)号：US07990999B2
公开(公告)日：2011-08-02
申请号：US12353906
申请日：2009-01-14
申请人： Khee Wooi Lee , Mikal C. Hunsaker , Darren L. Abramson
发明人： Khee Wooi Lee , Mikal C. Hunsaker , Darren L. Abramson
IPC分类号： H04J3/02 , G06F13/14
CPC分类号： G06F13/364
摘要： Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input cycle streams. Each cycle stream contains a stream of requests of a given type and associated priority. Under normal circumstances in which resource buffer availability for a destination device is not an issue, higher priority streams are provided grants over lower priority streams, with all streams receiving grants. However, when a resource buffer is not available for a lower priority stream, arbitration of high priority streams with available buffer resources are redirected to the low priority arbitration pool, resulting in generation of grant counts for both the higher and lower priority streams. When the resource buffer for the low priority stream becomes available and a corresponding request is arbitrated in the high priority arbitration pool, a grant for the request can be immediately made since grant counts for the stream already exist.
摘要翻译：用于以防止饥饿的方式仲裁优先循环流的方法和装置。采用高优先级和低优先权仲裁池来仲裁多个输入循环流。每个循环流包含给定类型和相关优先级的请求流。在目标设备的资源缓冲区可用性不是问题的正常情况下，较高优先级流被提供给较低优先级的流，所有流都接收到许可。然而，当资源缓冲器不可用于较低优先级流时，具有可用缓冲器资源的高优先级流的仲裁被重定向到低优先级仲裁池，导致产生用于较高和较低优先级流的授权计数。当低优先级流的资源缓冲器变得可用并且在高优先级仲裁池中仲裁相应的请求时，可以立即进行该请求的许可，因为已经存在流的授权计数。

6. 发明授权

US06529980B1 Superposition of host bridge status onto an existing request/grant signaling protocol 失效
标题翻译：主桥状态叠加到现有的请求/授权信令协议上
公开(公告)号：US06529980B1
公开(公告)日：2003-03-04
申请号：US08784199
申请日：1997-01-15
申请人： Darren L. Abramson
发明人： Darren L. Abramson
IPC分类号： G06F100
CPC分类号： G06F13/4054 , G06F13/4031
摘要： A protocol for superimposing status information onto an arbitration scheme between a first bus agent and a second bus agent. One embodiment of the arbitration scheme uses a grant signal and a request signal to arbitrate for use of a bus. The second bus agent may request to use the bus by asserting a request signal, which is received by a bus arbitration circuit. The bus arbitration circuit may or may not reside within the first bus agent. The bus arbitration logic acknowledges the request by asserting a grant signal, which is received by the second bus agent. A specific relationship between an address phase and the arbitration signals allows the first bus agent to pass status information to the second bus agent via the grant signal. The specific relationship between an address phase and the arbitration signals is a condition that typically does not occur where the arbitration signals are used to arbitrate for use of the bus.
摘要翻译：一种用于将状态信息叠加到第一总线代理和第二总线代理之间的仲裁方案的协议。仲裁方案的一个实施例使用授权信号和请求信号仲裁使用总线。第二总线代理可以通过断言由总线仲裁电路接收到的请求信号来请求使用总线。总线仲裁电路可以或可以不驻留在第一总线代理内。总线仲裁逻辑通过断言由第二总线代理接收的授权信号来确认该请求。地址相位与仲裁信号之间的具体关系允许第一总线代理经由授权信号将状态信息传递给第二总线代理。地址相位与仲裁信号之间的具体关系是通常不会发生仲裁信号来仲裁使用总线的条件。

7. 发明授权

US08930602B2 Providing adaptive bandwidth allocation for a fixed priority arbiter 有权
标题翻译：为固定优先仲裁器提供自适应带宽分配
公开(公告)号：US08930602B2
公开(公告)日：2015-01-06
申请号：US13222354
申请日：2011-08-31
申请人： Kie Woon Lim , E-Liang Chew , Khee Wooi Lee , Darren L. Abramson
发明人： Kie Woon Lim , E-Liang Chew , Khee Wooi Lee , Darren L. Abramson
IPC分类号： G06F12/00 , G06F13/14 , G06F13/38 , G06F13/00 , G06F13/36 , G06F13/362
CPC分类号： G06F13/14 , G06F13/364
摘要： In one embodiment, the present invention includes a method for receiving requests from requestors in an arbiter, detecting that none of the requestors have a qualified request for at least one cycle of an arbitration round, and preventing a grant count reload of grant counters associated with the when at least one of the requestors has available grants for the arbitration round. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在仲裁器中接收来自请求者的请求的方法，检测到所有请求者都不具有至少一个仲裁循环周期的合格请求，并且防止授权计数重新加载与当至少有一个请求者有可用的仲裁通知时。描述和要求保护其他实施例。

8. 发明授权

US06499077B1 Bus interface unit for reflecting state information for a transfer request to a requesting device 有权
标题翻译：总线接口单元，用于将用于转发请求的状态信息反映到请求设备
公开(公告)号：US06499077B1
公开(公告)日：2002-12-24
申请号：US09475964
申请日：1999-12-30
申请人： Darren L. Abramson , Mikal C. Hunsaker
发明人： Darren L. Abramson , Mikal C. Hunsaker
IPC分类号： G06F1300
CPC分类号： G06F13/4059
摘要： A request interface device and method for operating the device and its components are described. The request interface device comprises a bus interface unit (BIU) and a requesting device. The requesting device generates a transfer request for data or command information, along with state information determining the manner in which the requester will transfer the data or command information associated with the request once the transfer request is granted. The transfer request and the associated state information are sent to the BIU, freeing the requester to generate new requests wile the first transfer request is waiting to be granted. The transfer request and associated information is stored in a queue within the BIU while the BIU logic gains access to the host bus. Once the transfer request is granted, it is sent over the host bus to its target while the associated state information is concurrently reflected back to the requestor to be used by the requester to complete the data or command information transfer.
摘要翻译：描述了用于操作设备及其组件的请求接口设备和方法。请求接口设备包括总线接口单元（BIU）和请求设备。请求设备生成数据或命令信息的传送请求，以及确定在授予传输请求之后请求者将传送数据或与请求相关联的命令信息的方式的状态信息。转移请求和相关联的状态信息被发送到BIU，释放请求者产生新的请求，这是第一个转移请求等待被授予的请求。传输请求和相关信息存储在BIU内的队列中，而BIU逻辑则可访问主机总线。一旦传输请求被授权，它将通过主机总线发送到其目标，而相关联的状态信息被同时反射回请求者以供请求者用于完成数据或命令信息传送。

9. 发明授权

US06385671B1 Method/apparatus for flushing DMA transmit packet in FIFO when self-ID code generated by counter after bus reset is different than FIFO message self-ID field 失效
标题翻译：在总线复位后由计数器产生的自身ID代码与FIFO消息自身ID字段不同时，用于刷新FIFO中的DMA发送分组的方法/装置
公开(公告)号：US06385671B1
公开(公告)日：2002-05-07
申请号：US09280781
申请日：1999-03-29
申请人： Mikal C. Hunsaker , Darren L. Abramson
发明人： Mikal C. Hunsaker , Darren L. Abramson
IPC分类号： G06F1300
CPC分类号： H04L49/9094 , G06F13/28 , H04L49/90 , H04L49/901
摘要： The present invention discloses a method and apparatus for processing a packet of data received from a direct memory access (DMA) engine. In one embodiment, a counter generates a self-ID code and increments the self-ID code after a bus reset. A formatter is coupled to the counter to format a start-of-packet (SOP) message which contains a self-ID field. The SOP message corresponds to the packet and the self-ID field corresponds to the self-ID code. A first-in-first-out (FIFO) is coupled to the formatter to store the SOP message and the packet. A comparator is coupled to the FIFO to compare the self-ID field of the message read from the FIFO with the self-ID code. A control circuit, which is coupled to the FIFO, flushes the packet if the self-ID field of the message is different than the self-ID code.
摘要翻译：本发明公开了一种用于处理从直接存储器访问（DMA）引擎接收的数据分组的方法和装置。在一个实施例中，计数器产生自身ID码并且在总线复位之后增加自身ID码。格式化器耦合到计数器以格式化包含自身ID字段的分组包（SOP）消息。 SOP消息对应于分组，并且自身ID字段对应于自身ID代码。先进先出（FIFO）耦合到格式器以存储SOP消息和分组。比较器耦合到FIFO以比较从FIFO读取的消息的自身ID字段与自身ID码。耦合到FIFO的控制电路如果消息的自身ID字段不同于自身ID码，则刷新分组。

10. 发明授权

US5991304A Method and apparatus for minimizing asynchronous transmit FIFO under-run and receive FIFO over-run conditions 失效
标题翻译：用于最小化异步传输FIFO欠运行和接收FIFO超载条件的方法和装置
公开(公告)号：US5991304A
公开(公告)日：1999-11-23
申请号：US23394
申请日：1998-02-13
申请人： Darren L. Abramson
发明人： Darren L. Abramson
IPC分类号： G06F20060101 , H04J20060101 , H04J3/26 , H04L12/00
CPC分类号： G06F13/385
摘要： A circuit adapted to a first-in/first-out device ("FIFO") is disclosed. The circuit includes a counter and a first end of packet detector that is coupled to the counter. The first end of packet detector increments the counter if an end of packet is detected at an input of the FIFO. The circuit also includes a second end of packet detector coupled to the counter. The second end of packet detector decrements the counter if an end of packet is detected at an output of the FIFO. A detector circuit is coupled to an output of the counter and requests a bus transaction in response to the output of the counter. In another aspect, the present invention is a method of preventing data over-run errors in a receive FIFO having an input and an output. The method includes the steps of monitoring an input of the receive FIFO to determine a number of data packets received, monitoring an output of the receive FIFO for an end of packet to determine a number of data packets drained, and asserting a busy acknowledge line if the difference between the number of data packets received and the number of data packets drained is greater than and alternatively equal to a predetermined value.
摘要翻译：公开了一种适用于先入/先出设备（“FIFO”）的电路。电路包括计数器和耦合到计数器的分组检测器的第一端。如果在FIFO的输入端检测到分组的结尾，则分组检测器的第一端增加计数器。电路还包括耦合到计数器的分组检测器的第二端。如果在FIFO的输出端检测到分组的结尾，则分组检测器的第二端将计数器递减。检测器电路耦合到计数器的输出端，并响应于计数器的输出请求总线事务。在另一方面，本发明是一种在具有输入和输出的接收FIFO中防止数据过运行错误的方法。该方法包括以下步骤：监视接收FIFO的输入以确定接收到的数据分组的数量，监视接收FIFO的输出以用于分组结束以确定耗尽的数据分组的数量，并且断言忙确认行if 所接收的数据分组的数量与排出的数据分组的数量之间的差异大于或者等于预定值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式