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1. 发明授权

US07701791B2 Low read current architecture for memory 有权
标题翻译：低读取存储体系结构
公开(公告)号：US07701791B2
公开(公告)日：2010-04-20
申请号：US11881500
申请日：2007-07-26
申请人： Darrell Rinerson , Christophe J. Chevallier , Chang Hua Siau
发明人： Darrell Rinerson , Christophe J. Chevallier , Chang Hua Siau
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C13/0007 , G11C13/0026 , G11C13/004 , G11C13/0061 , G11C13/02 , G11C2013/0054 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77
摘要： A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
摘要翻译：用于存储器的低读取当前体系结构。允许交叉点存储器阵列的位线被选择的字线充电，直到确保存储器状态和参考电平之间的最小电压差。

2. 发明申请

US20100157647A1 Memory access circuits and layout of the same for cross-point memory arrays 审中-公开
标题翻译：存储器访问电路和布局相同的交叉点存储器阵列
公开(公告)号：US20100157647A1
公开(公告)日：2010-06-24
申请号：US12653898
申请日：2009-12-18
申请人： Darrell Rinerson , Christophe J. Chevallier , Chang Hua Siau
发明人： Darrell Rinerson , Christophe J. Chevallier , Chang Hua Siau
IPC分类号： G11C5/02 , H01L27/00 , G11C8/10
CPC分类号： G11C8/10 , G11C5/02 , G11C5/025 , H01L27/0688
摘要： An integrated circuit includes a substrate including active circuitry fabricated on the substrate and a cross-point memory array formed above the substrate. The cross-point memory array can include conductive array lines arranged in different directions, and re-writable memory cells. Further, the integrated circuit can also include a memory access circuit configured to perform data operations on the cross-point memory array. The integrated circuit can include a cross-point memory array interface layer positioned between the substrate and the cross-point array and including conductive paths configured to electrically couple portions of the memory access circuit with a subset of the conductive array lines. At least one layer of cross-point memory arrays can be formed over the substrate. The memory cells can be two-terminal memory cells that store data as a plurality of conductivity profiles (e.g., resistive states) that can be non-destructively determined by applying a read voltage across the terminals.
摘要翻译：集成电路包括：衬底，其包括在衬底上制造的有源电路和形成在衬底上方的交叉点存储器阵列。交叉点存储器阵列可以包括布置在不同方向的导电阵列线以及可重写存储器单元。此外，集成电路还可以包括被配置为在交叉点存储器阵列上执行数据操作的存储器访问电路。集成电路可以包括位于衬底和交叉点阵列之间的交叉点存储器阵列接口层，并且包括被配置为将存储器访问电路的一部分与导电阵列线的子集电耦合的导电路径。可以在衬底上形成至少一层交叉点存储器阵列。存储器单元可以是将数据存储为可以通过跨终端施加读取电压而非破坏性地确定的多个电导率分布（例如电阻状态）的两端存储单元。

3. 发明授权

US07505347B2 Method for sensing a signal in a two-terminal memory array having leakage current 有权
标题翻译：用于感测具有漏电流的双端存储器阵列中的信号的方法
公开(公告)号：US07505347B2
公开(公告)日：2009-03-17
申请号：US12072813
申请日：2008-02-28
申请人： Darrell Rinerson , Christophe J. Chevallier , Chang Hua Siau
发明人： Darrell Rinerson , Christophe J. Chevallier , Chang Hua Siau
IPC分类号： G11C7/02
CPC分类号： G11C11/16 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2013/0054 , G11C2013/0057 , G11C2211/5634 , G11C2213/31 , G11C2213/32 , G11C2213/34 , G11C2213/77
摘要： A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
摘要翻译：双端存储器阵列包括多个第一和第二导电迹线。地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读取操作中由感测单元感测。总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。

4. 发明授权

US07436723B2 Method for two-cycle sensing in a two-terminal memory array having leakage current 有权
标题翻译：具有漏电流的双端存储器阵列中的双周期感测方法
公开(公告)号：US07436723B2
公开(公告)日：2008-10-14
申请号：US12074448
申请日：2008-03-03
申请人： Darrell Rinerson , Christophe J. Chevallier , Chang Hua Siau
发明人： Darrell Rinerson , Christophe J. Chevallier , Chang Hua Siau
IPC分类号： G11C7/02
CPC分类号： G11C11/16 , G11C13/004 , G11C2013/0057
摘要： A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.
摘要翻译：双端存储器阵列包括多个第一和第二导电迹线。地址单元可操作地对所选择的第一和第二导电迹线对施加选择电压，并将非选择电压电势施加到未选择的迹线。在所选择的第一导电迹线中流动的总电流和流过未选择的第二导电迹线的漏电流在一个周期或两个周期的预读取操作中由感测单元感测。总和漏电流可以与参考信号组合以导出指示表示存储的数据的多个电导率分布之一的数据信号。电导率分布可以存储在与所选择的第一和第二导电迹线电串联的电阻状态存储元件中。

5. 发明申请

US20110188282A1 Memory architectures and techniques to enhance throughput for cross-point arrays 有权
标题翻译：内存架构和技术，以增强交叉点阵列的吞吐量
公开(公告)号：US20110188282A1
公开(公告)日：2011-08-04
申请号：US12658138
申请日：2010-02-02
申请人： Christophe J. Chevallier , Sri Namala , Chang Hua Siau , David Eggleston
发明人： Christophe J. Chevallier , Sri Namala , Chang Hua Siau , David Eggleston
IPC分类号： G11C5/02 , H01L21/8239 , G11C8/10
CPC分类号： H01L27/1052 , G11C5/025 , G11C5/04 , G11C5/063 , G11C5/066 , G11C8/10 , H01L27/0207 , H01L27/0688
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement memory architectures configured to enhance throughput for cross point arrays including memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes arrays that include memory elements being formed BEOL above a FEOL logic layer within a boundary in a plane parallel to a substrate, and array lines. Further, the integrated circuit includes array line decoders disposed in the logic layer within a region located coextensive with the boundary and between the substrate and the arrays. In some embodiments, the disposition of peripheral circuitry, such as the array line decoders, under the arrays can preserve or optimize die efficiency for throughput enhancement.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，其被配置为增强包括诸如基于第三维存储器技术的存储器元件的存储器元件的交叉点阵列的吞吐量。在至少一些实施例中，集成电路包括阵列，其包括在与基板平行的平面内的边界内的FEOL逻辑层上形成BEOL的阵列线和阵列线。此外，集成电路包括布置在逻辑层内的阵列线解码器，该阵列线路解码器位于与边界共同延伸并且在基板和阵列之间的区域内。在一些实施例中，在阵列之下的外围电路（例如阵列线解码器）的布置可以保持或优化用于吞吐量增强的管芯效率。

6. 发明申请

US20110188284A1 Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory 有权
标题翻译：补偿存储器访问信号的电路和技术，用于在多层存储器中的参数变化
公开(公告)号：US20110188284A1
公开(公告)日：2011-08-04
申请号：US12931438
申请日：2011-02-01
申请人： Christophe J. Chevallier , Seow Fong Lim , Chang Hua Siau
发明人： Christophe J. Chevallier , Seow Fong Lim , Chang Hua Siau
IPC分类号： G11C5/02 , G11C7/00 , G11C11/00
CPC分类号： G11C7/22 , B82Y30/00 , G11C5/02 , G11C7/04 , G11C8/10 , G11C8/12 , G11C11/21 , G11C13/0021
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地，涉及用于实现电路的系统，集成电路和方法，所述电路被配置为通过在存储器操作期间调整存取信号来补偿存储器层中的参数变化。在一些实施例中，存储器单元基于第三维存储器技术。在至少一些实施例中，集成电路包括多层存储器，包括半导体材料子层的层。集成电路还包括被配置为生成访问信号以便于访问操作的访问信号发生器，以及被配置为调整多层存储器中的每层的访问信号的特征调整器。

7. 发明申请

US20110188283A1 Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross-point arrays 有权
标题翻译：用于补偿数据信号的电路和技术，用于影响交叉点阵列中的存储器单元的参数变化
公开(公告)号：US20110188283A1
公开(公告)日：2011-08-04
申请号：US12931422
申请日：2011-01-31
申请人： Christophe J. Chevallier , Seow Fong Lim , Chang Hua Siau
发明人： Christophe J. Chevallier , Seow Fong Lim , Chang Hua Siau
IPC分类号： G11C5/02 , G11C11/21 , B82Y30/00
CPC分类号： G11C7/22 , B82Y30/00 , G11C5/02 , G11C7/04 , G11C8/10 , G11C8/12 , G11C11/21 , G11C13/0021
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point array comprising memory elements disposed among word lines and bit lines, where a parameter can affect the operating characteristics of a memory element. The integrated circuit further includes a data signal adjuster configured to modify the operating characteristic to compensate for a deviation from a target value for the operating characteristic based on the parameter. In some embodiments, the memory element, such as a resistive memory element, is configured to generate a data signal having a magnitude substantially at the target value independent of variation in the parameter.
摘要翻译：本发明的实施例大体上涉及半导体和存储器技术，更具体地，涉及用于实现电路的系统，集成电路和方法，其被配置为补偿影响存储器元件的操作的参数变化，诸如基于第三维存储器的存储器元件技术。在至少一些实施例中，集成电路包括交叉点阵列，其包括布置在字线和位线之间的存储器元件，其中参数可影响存储器元件的操作特性。集成电路还包括数据信号调整器，其被配置为基于该参数来修改操作特性以补偿与操作特性的目标值的偏差。在一些实施例中，诸如电阻性存储器元件的存储器元件被配置为生成具有与参数变化无关的基本上在目标值的幅度的数据信号。

8. 发明授权

US08427868B2 Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory 有权
公开(公告)号：US08427868B2
公开(公告)日：2013-04-23
申请号：US12931438
申请日：2011-02-01
申请人： Christophe J. Chevallier , Seow Fong Lim , Chang Hua Siau
发明人： Christophe J. Chevallier , Seow Fong Lim , Chang Hua Siau
IPC分类号： G11C11/34
CPC分类号： G11C7/22 , B82Y30/00 , G11C5/02 , G11C7/04 , G11C8/10 , G11C8/12 , G11C11/21 , G11C13/0021
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

9. 发明授权

US08363443B2 Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross-point arrays 有权
标题翻译：用于补偿数据信号的电路和技术，用于影响交叉点阵列中的存储器单元的参数变化
公开(公告)号：US08363443B2
公开(公告)日：2013-01-29
申请号：US12931422
申请日：2011-01-31
申请人： Christophe J. Chevallier , Seow Fong Lim , Chang Hua Siau
发明人： Christophe J. Chevallier , Seow Fong Lim , Chang Hua Siau
IPC分类号： G11C5/02 , G11C11/21
CPC分类号： G11C7/22 , B82Y30/00 , G11C5/02 , G11C7/04 , G11C8/10 , G11C8/12 , G11C11/21 , G11C13/0021
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point array comprising memory elements disposed among word lines and bit lines, where a parameter can affect the operating characteristics of a memory element. The integrated circuit further includes a data signal adjuster configured to modify the operating characteristic to compensate for a deviation from a target value for the operating characteristic based on the parameter. In some embodiments, the memory element, such as a resistive memory element, is configured to generate a data signal having a magnitude substantially at the target value independent of variation in the parameter.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地，涉及用于实现电路的系统，集成电路和方法，所述电路被配置为补偿影响存储器元件的操作的参数变化，诸如基于第三维存储器的存储器元件技术。在至少一些实施例中，集成电路包括交叉点阵列，其包括布置在字线和位线之间的存储器元件，其中参数可影响存储器元件的操作特性。集成电路还包括数据信号调整器，其被配置为基于该参数来修改操作特性以补偿与操作特性的目标值的偏差。在一些实施例中，诸如电阻性存储器元件的存储器元件被配置为生成具有与参数变化无关的基本上在目标值的幅度的数据信号。

10. 发明授权

US07830701B2 Contemporaneous margin verification and memory access for memory cells in cross point memory arrays 有权
标题翻译：交叉点存储器阵列中存储单元的同期保证金验证和存储器访问
公开(公告)号：US07830701B2
公开(公告)日：2010-11-09
申请号：US12284227
申请日：2008-09-19
申请人： Chang Hua Siau , Christophe J. Chevallier
发明人： Chang Hua Siau , Christophe J. Chevallier
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C16/3418 , G11C16/3431 , G11C2013/0054 , G11C2211/5634 , G11C2211/5646 , G11C2213/71 , G11C2213/77
摘要： Circuitry and methods for restoring data values in non-volatile memory are disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory cells. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory cells substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory cells may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).
摘要翻译：公开了用于恢复非易失性存储器中的数据值的电路和方法。集成电路包括存储器访问电路和被配置为在至少一个两端非易失性交叉点存储器阵列的读取操作期间感测数据信号的感测电路。每个存储器阵列包括多个两端存储单元。可以在衬底上制造多个存储器阵列并且彼此垂直地堆叠。此外，集成电路可以包括边缘管理器电路，其被配置为基本上在读取操作期间管理两端存储器单元的读取余量，从而提供同时的读取和余量确定操作。从两端存储单元读取的存储数据可以具有恢复的存储数据的值（例如，重新写入同一单元或另一单元），如果该值不与读取余量相关联（例如，硬编程或硬擦除状态）。

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