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1. 发明授权

US5537600A Personal computer with alternate system controller 失效
标题翻译：具有备用系统控制器的个人计算机
公开(公告)号：US5537600A
公开(公告)日：1996-07-16
申请号：US706425
申请日：1991-05-28
申请人： Daniel P. Fuoco , Luis A. Hernandez , Eric Mathisen , Dennis L. Moeller , Jonathan H. Raymond , Esmaeil Tashakori
发明人： Daniel P. Fuoco , Luis A. Hernandez , Eric Mathisen , Dennis L. Moeller , Jonathan H. Raymond , Esmaeil Tashakori
IPC分类号： G06F13/38 , G06F1/24 , G06F13/40 , G06F15/76
CPC分类号： G06F13/4063
摘要： This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.
摘要翻译：本发明涉及个人计算机，更具体地说涉及个人计算机，其中为常规系统控制处理器提供能力被复位，初始化并且如果为系统提供替代系统控制器则被隔离。根据本发明，个人计算机系统具有高速局部处理器数据总线; 输入/输出数据总线; 直接耦合到本地处理器总线的微处理器; 连接器，其直接连接到本地处理器总线，用于接收替代处理器的接收; 以及总线接口控制器，其直接耦合到本地处理器总线并且直接耦合到输入/输出数据总线，用于在本地处理器总线和输入/输出数据总线之间提供通信，总线接口控制器提供用于检测存在接收器中接收的替代处理器，并且响应于检测到替代处理器的存在，将本地处理器总线的控制从微处理器传送到备用处理器。

2. 发明授权

US5353417A Personal computer with bus interface controller coupled directly with local processor and input/output data buses and for anticipating memory control changes on arbitration for bus access 失效
标题翻译：具有总线接口控制器的个人计算机与本地处理器和输入/输出数据总线直接耦合，并用于预测总线访问仲裁时的存储器控制变化
公开(公告)号：US5353417A
公开(公告)日：1994-10-04
申请号：US706534
申请日：1991-05-28
申请人： Daniel P. Fuoco , Luis A. Hernandez , Eric Mathisen , Dennis L. Moeller , Jonathan H. Raymond , Esmaeil Tashakori
发明人： Daniel P. Fuoco , Luis A. Hernandez , Eric Mathisen , Dennis L. Moeller , Jonathan H. Raymond , Esmaeil Tashakori
IPC分类号： G06F13/18 , G06F13/36 , G06F13/362 , G06F13/00 , G06F12/00
CPC分类号： G06F13/362
摘要： This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.
摘要翻译：本发明涉及个人计算机，更具体地涉及个人计算机，其中在数据处理总线上进行控制的仲裁发生在直接与总线耦合的多个“主”设备和存储器地址信号之间，以响应于这种仲裁而变化。个人计算机系统具有高速本地处理器数据总线，输入/输出数据总线，直接连接到本地处理器总线的微处理器，耦合到本地处理器总线的易失性存储器，用于数据的易失性存储，以及总线接口控制器直接到本地处理器总线，并直接连接到输入/输出数据总线，以提供总线之间的通信。总线接口控制器提供直接耦合到输入/输出数据总线的设备之间的仲裁，用于访问输入/输出数据总线和本地处理器总线，并且在输入/输出数据总线和所述微处理器之间进行仲裁以访问本地处理器总线。总线接口控制器还耦合到易失性存储器，用于向易失性存储器提供行地址选择信号，从而选择要访问的数据存储区域，并通过改变行地址选择信号来响应授予局部总线的访问变化提供给易失性存储器以准备访问易失性存储器的潜在不同的数据存储区域。

3. 发明授权

US5630078A Personal computer with processor reset control 失效
标题翻译：具有处理器复位控制的个人计算机
公开(公告)号：US5630078A
公开(公告)日：1997-05-13
申请号：US262397
申请日：1994-06-20
申请人： Daniel P. Fuoco , Luis A. Hernandez , Eric Mathisen , Dennis L. Moeller , Jonathan H. Raymond , Esmaeil Tashakori
发明人： Daniel P. Fuoco , Luis A. Hernandez , Eric Mathisen , Dennis L. Moeller , Jonathan H. Raymond , Esmaeil Tashakori
IPC分类号： G06F1/24 , G06F13/00 , G06F13/14
CPC分类号： G06F1/24
摘要： This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.
摘要翻译：本发明涉及个人计算机，更具体地说，涉及个人计算机，其中提供能力以通过发生RESET信号来继续处理，同时避免系统故障。个人计算机系统具有高速本地处理器数据总线; 输入/输出数据总线; 直接耦合到本地处理器总线的可复位微处理器; 以及总线接口控制器，其直接耦合到本地处理器总线，并且直接耦合到输入/输出数据总线，用于在本地处理器总线和输入/输出数据总线之间提供通信。总线接口控制器提供直接耦合到输入/输出数据总线的设备之间的仲裁，以访问输入/输出数据总线和本地处理器总线，并在输入/输出数据总线和微处理器之间进行仲裁以访问本地处理器总线。总线接口控制器进一步识别接收到用于启动微处理器的复位的复位信号，并且延迟复位信号的传送，直到总线接口控制器禁止通过任何设备来访问本地处理器总线和输入/输出总线可能请求这样的访问。

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