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1. 发明授权

US5537600A Personal computer with alternate system controller 失效
标题翻译：具有备用系统控制器的个人计算机
公开(公告)号：US5537600A
公开(公告)日：1996-07-16
申请号：US706425
申请日：1991-05-28
申请人： Daniel P. Fuoco , Luis A. Hernandez , Eric Mathisen , Dennis L. Moeller , Jonathan H. Raymond , Esmaeil Tashakori
发明人： Daniel P. Fuoco , Luis A. Hernandez , Eric Mathisen , Dennis L. Moeller , Jonathan H. Raymond , Esmaeil Tashakori
IPC分类号： G06F13/38 , G06F1/24 , G06F13/40 , G06F15/76
CPC分类号： G06F13/4063
摘要： This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.
摘要翻译：本发明涉及个人计算机，更具体地说涉及个人计算机，其中为常规系统控制处理器提供能力被复位，初始化并且如果为系统提供替代系统控制器则被隔离。根据本发明，个人计算机系统具有高速局部处理器数据总线; 输入/输出数据总线; 直接耦合到本地处理器总线的微处理器; 连接器，其直接连接到本地处理器总线，用于接收替代处理器的接收; 以及总线接口控制器，其直接耦合到本地处理器总线并且直接耦合到输入/输出数据总线，用于在本地处理器总线和输入/输出数据总线之间提供通信，总线接口控制器提供用于检测存在接收器中接收的替代处理器，并且响应于检测到替代处理器的存在，将本地处理器总线的控制从微处理器传送到备用处理器。

2. 发明授权

US5388156A Personal computer system with security features and method 失效
标题翻译：具有安全功能和方法的个人计算机系统
公开(公告)号：US5388156A
公开(公告)日：1995-02-07
申请号：US840965
申请日：1992-02-26
申请人： John W. Blackledge, Jr. , Grant L. Clarke, Jr. , Richard A. Dayan , Kimthanh D. Le , Patrick E. McCourt , Matthew T. Mittelstedt , Dennis L. Moeller , Palmer E. Newman , David L. Randall , JoAnna B. Yoder
发明人： John W. Blackledge, Jr. , Grant L. Clarke, Jr. , Richard A. Dayan , Kimthanh D. Le , Patrick E. McCourt , Matthew T. Mittelstedt , Dennis L. Moeller , Palmer E. Newman , David L. Randall , JoAnna B. Yoder
IPC分类号： G06F11/00 , G06F9/06 , G06F12/14 , G06F21/00 , G06F21/06 , G06F21/22 , G06F21/24 , H04L9/00
CPC分类号： G06F21/86 , G06F2211/009 , G06F2221/2143
摘要： This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. In particular, a personal computer system in accordance with this invention has a normally closed enclosure, at least one erasable memory element for selective activation to active and inactive states and for receiving and storing a privileged access password when in the active state, an option switch operatively connected with the erasable memory element for setting the erasable memory element to the active and inactive states, a tamper detection switch operatively connected with the erasable memory element for detecting opening of the enclosure and for invalidating any privileged access password stored in the erasable memory element in response to any switching of the tamper switch, and a system processor operatively connected with the erasable memory element for controlling access to at least certain levels of data stored within the system by distinguishing between the active and inactive states of the memory element and between entry and non-entry of any stored privileged access password. In the presently preferred form of the invention, two non-volatile erasable memory elements are provided, one an EEPROM and the other battery backed CMOS RAM.
摘要翻译：本发明涉及个人计算机系统，更具体地说，涉及具有能够控制对这种系统中保留的数据的访问的安全特征的这种系统。特别地，根据本发明的个人计算机系统具有常闭壳体，至少一个可擦除存储器元件，用于选择性地激活到主动和非活动状态，并且在处于活动状态时接收和存储特权访问密码，选项开关与可擦除存储器元件可操作地连接，用于将可擦除存储器元件设置为活动和非活动状态;篡改检测开关，其可操作地与可擦除存储元件连接，用于检测外壳的打开并使存储在可擦除存储器元件中的任何特权访问密码无效响应于所述篡改开关的任何切换，以及与所述可擦除存储器元件可操作地连接的系统处理器，用于通过区分所述存储元件的有效和非活动状态以及在进入之间来控制对存储在所述系统内的至少某一级别的数据的访问并且不输入任何存储的特权访问权限 ss字。在本发明的当前优选形式中，提供了两个非易失性可擦除存储器元件，一个是EEPROM和另一个电池支持的CMOS RAM。

3. 发明授权

US5341422A Trusted personal computer system with identification 失效
标题翻译：具有识别能力的个人计算机系统
公开(公告)号：US5341422A
公开(公告)日：1994-08-23
申请号：US947014
申请日：1992-09-17
申请人： John W. Blackledge, Jr. , Richard A. Dayan , Dennis L. Moeller , Palmer E. Newman , Kenneth J. P. Zubay
发明人： John W. Blackledge, Jr. , Richard A. Dayan , Dennis L. Moeller , Palmer E. Newman , Kenneth J. P. Zubay
IPC分类号： G06F12/14 , G06F1/00 , G06F21/02 , G06F21/24 , H04L9/00
CPC分类号： G06F21/82 , G06F21/86 , G06F2211/007 , G06F2211/009
摘要： This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. This invention contemplates protecting a personal computer system which has the capability of becoming a secure system from being placed into that condition by an attack on an unsecured machine. Additionally, in a network environment, it is important to maintaining network security that any given particular system be uniquely identified to the network, in order to guard against the substitution of an insecure "alternate" which would open the network to attack through an insecure system. This invention contemplates provision for such identification in a secure manner.
摘要翻译：本发明涉及个人计算机系统，更具体地说，涉及具有能够控制对这种系统中保留的数据的访问的安全特征的这种系统。本发明考虑到保护具有成为安全系统的能力的个人计算机系统，以免受到不安全机器的攻击而被置于该状态。另外，在网络环境中，保持网络安全性至关重要，任何给定的特定系统可以被唯一地标识到网络，以防止替代不安全的“备用”，这将打开网络以通过不安全的系统进行攻击。本发明考虑以安全的方式提供这种识别。

4. 发明授权

US5327531A Data processing system including corrupt flash ROM recovery 失效
标题翻译：数据处理系统包括损坏的闪存ROM恢复
公开(公告)号：US5327531A
公开(公告)日：1994-07-05
申请号：US948053
申请日：1992-09-21
申请人： Richard Bealkowski , Dhruvkumar M. Desai , Robert B. Haig , Dennis L. Moeller , Essy Tashakori
发明人： Richard Bealkowski , Dhruvkumar M. Desai , Robert B. Haig , Dennis L. Moeller , Essy Tashakori
IPC分类号： G06F9/445 , G06F11/14 , G11C29/00 , G06F15/62
CPC分类号： G11C29/74 , G06F11/1417 , G06F8/66
摘要： A personal computer is provided with primary and secondary non-volatile storage devices for initializing the system when power is turned on. The primary device is a flash RAM. A flash ROM memory controller include means to detect when the flash ROM becomes corrupted and to switch over to the secondary device for initialization allowing the flash ROM to be later reprogrammed.
摘要翻译：在个人计算机上设置有初级和次级非易失性存储设备，用于在接通电源时初始化系统。主要设备是闪存RAM。闪存ROM存储器控制器包括检测闪存ROM何时被破坏并且切换到辅助设备以进行初始化的装置，以使稍后的ROM重新编程。

5. 发明授权

US4598356A Data processing system including a main processor and a co-processor and co-processor error handling logic 失效
标题翻译：数据处理系统包括主处理器和协处理器以及协处理器错误处理逻辑
公开(公告)号：US4598356A
公开(公告)日：1986-07-01
申请号：US567296
申请日：1983-12-30
申请人： Mark E. Dean , Dennis L. Moeller
发明人： Mark E. Dean , Dennis L. Moeller
IPC分类号： G06F9/46 , G06F9/38 , G06F11/00 , G06F11/07 , G06F13/36 , G06F15/16 , G06F15/177 , G06F13/14 , G06F13/42
CPC分类号： G06F11/0745 , G06F11/0724 , G06F11/0793 , G06F9/3885
摘要： In a data processing system including a main processor and a co-processor, a logic circuit is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honor the interrupt before executing another co-processor instruction.
摘要翻译：在包括主处理器和协处理器的数据处理系统中，逻辑电路被耦合以接收协处理器的错误和繁忙输出，以在有源误差和忙信号的共同作用上产生中断输出，并锁存忙信号到主处理器，以确保主处理器在执行另一个协处理器指令之前将遵守中断。

6. 发明授权

US5630078A Personal computer with processor reset control 失效
标题翻译：具有处理器复位控制的个人计算机
公开(公告)号：US5630078A
公开(公告)日：1997-05-13
申请号：US262397
申请日：1994-06-20
申请人： Daniel P. Fuoco , Luis A. Hernandez , Eric Mathisen , Dennis L. Moeller , Jonathan H. Raymond , Esmaeil Tashakori
发明人： Daniel P. Fuoco , Luis A. Hernandez , Eric Mathisen , Dennis L. Moeller , Jonathan H. Raymond , Esmaeil Tashakori
IPC分类号： G06F1/24 , G06F13/00 , G06F13/14
CPC分类号： G06F1/24
摘要： This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.
摘要翻译：本发明涉及个人计算机，更具体地说，涉及个人计算机，其中提供能力以通过发生RESET信号来继续处理，同时避免系统故障。个人计算机系统具有高速本地处理器数据总线; 输入/输出数据总线; 直接耦合到本地处理器总线的可复位微处理器; 以及总线接口控制器，其直接耦合到本地处理器总线，并且直接耦合到输入/输出数据总线，用于在本地处理器总线和输入/输出数据总线之间提供通信。总线接口控制器提供直接耦合到输入/输出数据总线的设备之间的仲裁，以访问输入/输出数据总线和本地处理器总线，并在输入/输出数据总线和微处理器之间进行仲裁以访问本地处理器总线。总线接口控制器进一步识别接收到用于启动微处理器的复位的复位信号，并且延迟复位信号的传送，直到总线接口控制器禁止通过任何设备来访问本地处理器总线和输入/输出总线可能请求这样的访问。

7. 发明授权

US5432939A Trusted personal computer system with management control over initial program loading 失效
标题翻译：受信任的个人计算机系统具有对初始程序加载的管理控制
公开(公告)号：US5432939A
公开(公告)日：1995-07-11
申请号：US889324
申请日：1992-05-27
申请人： John W. Blackledge, Jr. , Richard A. Dayan , Dennis L. Moeller , Palmer E. Newman , Kenneth J. P. Zubay
发明人： John W. Blackledge, Jr. , Richard A. Dayan , Dennis L. Moeller , Palmer E. Newman , Kenneth J. P. Zubay
IPC分类号： G06F1/00 , G06F9/06 , G06F9/445 , G06F12/14 , G06F21/00 , G06F21/06 , G06F21/20 , G06F21/22 , G06F21/24 , G06F9/44
CPC分类号： G06F21/85 , G06F9/4401 , G06F12/1408
摘要： This invention relates to personal computer systems and, more particularly, to such a system having security features enabling control over access to data retained in such a system. The features here described include a prioritized initial loading program for enabling initial loading of an operating system from a selected one of a plurality of sources, the prioritized initial loading program normally designating an interpreter program as a final option default in the event of failure of access to an operating system from any other one of the plurality of sources; a security utility program for enabling a designated user to (a) selectively modify the initial loading program by specifying the number and priority order of the plurality of sources and (b) selectively modify the initial loading program by deleting the interpreter program from the plurality of sources; a master cryptographic key for use in encrypting and decrypting data processed by the system CPU; and a second security utility program for enabling a designated user to modify the master cryptographic key.
摘要翻译：本发明涉及个人计算机系统，更具体地说，涉及具有能够控制对这种系统中保留的数据的访问的安全特征的这种系统。这里描述的特征包括优先的初始加载程序，用于使得能够从多个源中的所选的一个源初始加载操作系统，优先化的初始加载程序通常将解释程序指定为在访问失败的情况下的最终选项默认值涉及来自所述多个源中的任何另一个的操作系统; 一种用于使指定用户能够（a）通过指定所述多个源的数量和优先级顺序来选择性地修改所述初始加载程序的安全实用程序，以及（b）通过从所述多个源中删除所述解释程序来选择性地修改所述初始加载程序来源用于加密和解密由系统CPU处理的数据的主密码密钥; 以及用于使指定用户能够修改主加密密钥的第二安全实用程序。

8. 发明授权

US4922451A Memory re-mapping in a microcomputer system 失效
标题翻译：微机系统内存重映射
公开(公告)号：US4922451A
公开(公告)日：1990-05-01
申请号：US391634
申请日：1989-08-07
申请人： Yuan-Chang Lo , Dennis L. Moeller , John J. Szarek
发明人： Yuan-Chang Lo , Dennis L. Moeller , John J. Szarek
IPC分类号： G06F11/22 , G11C29/00
CPC分类号： G11C29/76 , G06F11/2289 , G11C29/88
摘要： A microcomputer system has a first, low order address, memory soldered to the planar printed circuit board and can accept further memory pluggable into a socket on the board. At power on self test, the memories are tested, and, if an error is detected in the first memory, this memory is disabled by directing the lowest order memory addresses to the second memory and reducing the highest order addresses by the number of locations in the first memory.
摘要翻译：微型计算机系统具有第一低位地址，焊接到平面印刷电路板的存储器，并且可以接受可插拔到板上的插座中的另外的存储器。在通电自检时，测试存储器，如果在第一存储器中检测到错误，则通过将最低订单存储器地址引导到第二存储器并且将最高订单地址减少最多的位置数来禁止该存储器第一个记忆。

9. 发明授权

US5465332A Selectable 8/16 bit DMA channels for "ISA" bus 失效
标题翻译： “ISA”总线可选择8/16位DMA通道
公开(公告)号：US5465332A
公开(公告)日：1995-11-07
申请号：US947680
申请日：1992-09-21
申请人： Michael J. Deloye , Daniel P. Fuoco , Dennis L. Moeller
发明人： Michael J. Deloye , Daniel P. Fuoco , Dennis L. Moeller
IPC分类号： G06F13/28 , G06F13/00 , H01J3/00
CPC分类号： G06F13/28
摘要： In a personal computing system the function of the DMA controllers in the "AT" or "ISA" bus has been modified so that the system may select whether the 16-bit DMA channels are to be used as 8-bit DMA channels or 16-bit DMA channels. An 8/16-bit mode bit for each of the 16-bit DMA channels is written in a control register during the system Power On Self Test routine. Once the mode bit is written for each of the three 16-bit DMA channels, it may be read when the channel is active to select whether the channel is to operate as an 8-bit or 16-bit channel. With this mode bit information available, the page addressing may be selectively changed from 128k size pages to 64k size pages when a 16-bit DMA channel is to be converted to 8-bit. In addition, the byte addressing within a page may be changed from two byte addressing during 16-bit mode to single byte addressing during 8-bit mode.
摘要翻译：在个人计算系统中，“AT”或“ISA”总线中的DMA控制器的功能已经被修改，使得系统可以选择是否将16位DMA通道用作8位DMA通道或16位DMA通道，位DMA通道。在系统上电自检程序期间，将16位DMA通道中的每一个的8/16位模式位写入控制寄存器。一旦为三个16位DMA通道中的每一个写入模式位，当通道有效时可以读取模式位，以选择通道是作为8位还是16位通道运行。利用该模式位信息，当16位DMA通道将被转换为8位时，页寻址可以从128k大小页被选择性地改变为64k大小页。另外，在8位模式期间，页内的字节寻址可以从16位模式下的两字节寻址改变为单字节寻址。

10. 发明授权

US5353417A Personal computer with bus interface controller coupled directly with local processor and input/output data buses and for anticipating memory control changes on arbitration for bus access 失效
标题翻译：具有总线接口控制器的个人计算机与本地处理器和输入/输出数据总线直接耦合，并用于预测总线访问仲裁时的存储器控制变化
公开(公告)号：US5353417A
公开(公告)日：1994-10-04
申请号：US706534
申请日：1991-05-28
申请人： Daniel P. Fuoco , Luis A. Hernandez , Eric Mathisen , Dennis L. Moeller , Jonathan H. Raymond , Esmaeil Tashakori
发明人： Daniel P. Fuoco , Luis A. Hernandez , Eric Mathisen , Dennis L. Moeller , Jonathan H. Raymond , Esmaeil Tashakori
IPC分类号： G06F13/18 , G06F13/36 , G06F13/362 , G06F13/00 , G06F12/00
CPC分类号： G06F13/362
摘要： This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.
摘要翻译：本发明涉及个人计算机，更具体地涉及个人计算机，其中在数据处理总线上进行控制的仲裁发生在直接与总线耦合的多个“主”设备和存储器地址信号之间，以响应于这种仲裁而变化。个人计算机系统具有高速本地处理器数据总线，输入/输出数据总线，直接连接到本地处理器总线的微处理器，耦合到本地处理器总线的易失性存储器，用于数据的易失性存储，以及总线接口控制器直接到本地处理器总线，并直接连接到输入/输出数据总线，以提供总线之间的通信。总线接口控制器提供直接耦合到输入/输出数据总线的设备之间的仲裁，用于访问输入/输出数据总线和本地处理器总线，并且在输入/输出数据总线和所述微处理器之间进行仲裁以访问本地处理器总线。总线接口控制器还耦合到易失性存储器，用于向易失性存储器提供行地址选择信号，从而选择要访问的数据存储区域，并通过改变行地址选择信号来响应授予局部总线的访问变化提供给易失性存储器以准备访问易失性存储器的潜在不同的数据存储区域。

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