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1. 发明申请

US20060023507A1 Method of reducing disturbs in non-volatile memory 有权
公开(公告)号：US20060023507A1
公开(公告)日：2006-02-02
申请号：US11238911
申请日：2005-09-28
申请人： John Mangan , Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
发明人： John Mangan , Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
IPC分类号： G11C7/10 , G11C11/34
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

2. 发明申请

US20070076510A1 Method of Reducing Disturbs in Non-Volatile Memory 有权
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US20070076510A1
公开(公告)日：2007-04-05
申请号：US11538521
申请日：2006-10-04
申请人： John Mangan , Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
发明人： John Mangan , Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
IPC分类号： G11C8/00
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

3. 发明申请

US20050146933A1 Method of reducing disturbs in non-volatile memory 失效
公开(公告)号：US20050146933A1
公开(公告)日：2005-07-07
申请号：US11054084
申请日：2005-02-08
申请人： Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
发明人： Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
IPC分类号： G11C16/02 , G11C16/12 , G11C16/04
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

4. 发明授权

US06490200B2 Non-volatile memory with improved sensing and method therefor 有权
标题翻译：具有改进感测的非易失性存储器及其方法
公开(公告)号：US06490200B2
公开(公告)日：2002-12-03
申请号：US09924410
申请日：2001-08-07
申请人： Raul-Adrian Cernea , Rushyah Tang , Douglas Lee , Chi-Ming Wang , Daniel Guterman
发明人： Raul-Adrian Cernea , Rushyah Tang , Douglas Lee , Chi-Ming Wang , Daniel Guterman
IPC分类号： G11C1606
CPC分类号： G11C16/28 , G11C7/06 , G11C8/04 , G11C11/5621 , G11C11/5642 , G11C16/32 , G11C19/00 , G11C2211/5644 , G11C2211/5645
摘要： Floating gate memories such as EEPROM and flash EEPROM have the memory state of a memory cell thereof determined by sensing the conduction current of the cell. Inherent noise fluctuations in the conduction current during sensing are canceled out by averaging the sensing over a predetermined period of time. In one embodiment, as an integral part of the averaging process, the averaged conduction current is obtained directly as a digital memory state. Accuracy in sensing is therefore greatly improved by avoiding sensing noise with the current and avoiding having to resolve its memory state in the analog domain by comparison with another noisy reference current. In another embodiment, conventional sensing techniques are improved when sensing is made by comparison with a reference current by means of a symmetric, switched or non-switched capacitor differential amplifier.
摘要翻译：诸如EEPROM和闪存EEPROM的浮动存储器存储器通过感测单元的传导电流来确定其存储单元的存储状态。感测期间的传导电流的固有噪声波动通过在预定时间段内对感测进行平均而抵消。在一个实施例中，作为平均处理的组成部分，平均的导通电流被直接获得作为数字存储器状态。因此，通过避免使用电流感测噪声并避免必须通过与其他噪声参考电流进行比较来解决模拟域中的存储状态，从而大大提高了感测精度。在另一个实施例中，当通过对称，开关或非开关电容器差分放大器与参考电流进行比较来进行感测时，常规感测技术得到改进。

5. 发明授权

US06661708B2 Non-volatile memory with improved sensing and method therefor 有权
公开(公告)号：US06661708B2
公开(公告)日：2003-12-09
申请号：US10290558
申请日：2002-11-07
申请人： Raul-Adrian Cernea , Rushyah Tang , Douglas Lee , Chi-Ming Wang , Daniel Guterman
发明人： Raul-Adrian Cernea , Rushyah Tang , Douglas Lee , Chi-Ming Wang , Daniel Guterman
IPC分类号： G11C1606
CPC分类号： G11C16/28 , G11C7/06 , G11C8/04 , G11C11/5621 , G11C11/5642 , G11C16/32 , G11C19/00 , G11C2211/5644 , G11C2211/5645
摘要： Floating gate memories such as EEPROM and flash EEPROM have the memory state of a memory cell thereof determined by sensing the conduction current of the cell. Inherent noise fluctuations in the conduction current during sensing are canceled out by averaging the sensing over a predetermined period of time. In one embodiment, as an integral part of the averaging process, the averaged conduction current is obtained directly as a digital memory state. Accuracy in sensing is therefore greatly improved by avoiding sensing noise with the current and avoiding having to resolve its memory state in the analog domain by comparison with another noisy reference current. In another embodiment, conventional sensing techniques are improved when sensing is made by comparison with a reference current by means of a symmetric, switched or non-switched capacitor differential amplifier.

6. 发明授权

US6044019A Non-volatile memory with improved sensing and method therefor 有权
公开(公告)号：US6044019A
公开(公告)日：2000-03-28
申请号：US177809
申请日：1998-10-23
申请人： Raul-Adrian Cernea , Rushyah Tang , Douglas Lee , Chi-Ming Wang , Daniel Guterman
发明人： Raul-Adrian Cernea , Rushyah Tang , Douglas Lee , Chi-Ming Wang , Daniel Guterman
IPC分类号： G11C16/06 , G11C11/56 , G11C16/02 , G11C16/28 , G11C13/00
CPC分类号： G11C11/5642 , G11C11/5621 , G11C16/28 , G11C16/32 , G11C19/00 , G11C2211/5644 , G11C2211/5645 , G11C7/06 , G11C8/04
摘要： Floating gate memories such as EEPROM and flash EEPROM have the memory state of a memory cell thereof determined by sensing the conduction current of the cell. Inherent noise fluctuations in the conduction current during sensing are canceled out by averaging the sensing over a predetermined period of time. In one embodiment, as an integral part of the averaging process, the averaged conduction current is obtained directly as a digital memory state. Accuracy in sensing is therefore greatly improved by avoiding sensing noise with the current and avoiding having to resolve its memory state in the analog domain by comparison with another noisy reference current. In another embodiment, conventional sensing techniques are improved when sensing is made by comparison with a reference current by means of a symmetric, switched or non-switched capacitor differential amplifier. The improved sensing accuracy allows higher resolution of conduction states, thereby allowing a cell to store substantially more than one bit of information.

7. 发明授权

US06282120B1 Non-volatile memory with improved sensing and method therefor 有权
标题翻译：具有改进感测的非易失性存储器及其方法
公开(公告)号：US06282120B1
公开(公告)日：2001-08-28
申请号：US09536930
申请日：2000-03-27
申请人： Raul-Adrian Cernea , Rushyah Tang , Douglas Lee , Chi-Ming Wang , Daniel Guterman
发明人： Raul-Adrian Cernea , Rushyah Tang , Douglas Lee , Chi-Ming Wang , Daniel Guterman
IPC分类号： G11C1606
CPC分类号： G11C11/5642 , G11C7/06 , G11C8/04 , G11C11/5621 , G11C16/28 , G11C16/32 , G11C19/00 , G11C2211/5644 , G11C2211/5645
摘要： Floating gate memories such as EEPROM and flash EEPROM have the memory state of a memory cell thereof determined by sensing the conduction current of the cell Inherent noise fluctuations in the conduction current during sensing are canceled out by averaging the sensing over a predetermined period of time. In one embodiment, as an integral part of the averaging process, the averaged conduction current is obtained directly as a digital memory state. Accuracy in sensing is therefore greatly improved by avoiding sensing noise with the current and avoiding having to resolve its memory state in the analog domain by comparison with another noisy reference current. In another embodiment, conventional sensing techniques are improved when sensing is made by comparison with a reference current by means of a symmetric, switched or non-switched capacitor differential amplifier. The improved sensing accuracy allows higher resolution of conduction states, thereby allowing a cell to store substantially more than one bit of information.
摘要翻译：诸如EEPROM和闪存EEPROM的浮动存储器存储器通过感测单元的传导电流来确定其存储单元的存储状态。通过在预定时间段内平均感测来抵消感测期间传导电流的固有噪声波动。在一个实施例中，作为平均处理的组成部分，平均的导通电流被直接获得作为数字存储器状态。因此，通过避免使用电流感测噪声并避免必须通过与其他噪声参考电流进行比较来解决模拟域中的存储状态，从而大大提高了感测精度。在另一个实施例中，当通过对称，开关或非开关电容器差分放大器与参考电流进行比较来进行感测时，常规感测技术得到改进。改进的感测精度允许更高的导通状态分辨率，从而允许单元存储大致多于一位的信息。

8. 发明申请

US20080116509A1 Multi-State Non-Volatile Integrated Circuit Memory Systems that Employ Dielectric Storage Elements 有权
公开(公告)号：US20080116509A1
公开(公告)日：2008-05-22
申请号：US12020266
申请日：2008-01-25
申请人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
发明人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/4234 , H01L29/7923 , Y10S438/947
摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

9. 发明申请

US20050157551A1 Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements 有权
公开(公告)号：US20050157551A1
公开(公告)日：2005-07-21
申请号：US11075427
申请日：2005-03-07
申请人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
发明人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
IPC分类号： G11C11/56 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/4234 , H01L29/7923 , Y10S438/947
摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

10. 发明申请

US20050180210A1 Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements 有权
公开(公告)号：US20050180210A1
公开(公告)日：2005-08-18
申请号：US11075423
申请日：2005-03-07
申请人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
发明人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
IPC分类号： G11C11/56 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/4234 , H01L29/7923 , Y10S438/947
摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

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