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1. 发明授权

US07499106B1 Method and system for synchronizing video information derived from an asynchronously sampled video signal 有权
标题翻译：用于同步从异步采样的视频信号导出的视频信息的方法和系统
公开(公告)号：US07499106B1
公开(公告)日：2009-03-03
申请号：US11082346
申请日：2005-03-17
申请人： Daniel Gudmunson , John Melanson , Rahul Singh , Ahsan Chowdhury
发明人： Daniel Gudmunson , John Melanson , Rahul Singh , Ahsan Chowdhury
IPC分类号： H04L7/00
CPC分类号： H03L7/1974 , H03L7/08 , H03L7/0805 , H03L2207/50 , H04N5/12 , H04N5/213 , H04N5/765 , H04N5/85 , H04N7/0132 , H04N9/8042 , H04N9/896 , H04N21/4325 , H04N21/44004
摘要： A method and system for synchronizing video information derived from an asynchronously sampled video signals provide a mechanism for using asynchronous sampling in the front-end of digital video capture systems. A ratio between the sampling clock frequency and the source video clock frequency is computed via an all digital phase-lock loop (ADPLL) and either a video clock is generated from the ratio by another PLL, a number to clock converter or the ratio is used directly to provide digital synchronization information to downstream processing blocks. A sample rate converter (SRC) is provided in an interpolator that either acts as a sample position corrector at the same line rate as the received video, or by introducing an offset in the ADPLL, the video data can be converted to another line rate via the SRC.
摘要翻译：用于同步从异步采样的视频信号导出的视频信息的方法和系统提供了在数字视频采集系统的前端中使用异步采样的机制。通过全数字锁相环（ADPLL）计算采样时钟频率和源视频时钟频率之间的比例，并且视频时钟由另一个PLL的比率，数字到时钟转换器或使用的比率产生直接向下游处理块提供数字同步信息。在内插器中提供采样率转换器（SRC），其作为采样位置校正器以与接收的视频相同的线路速率，或者通过在ADPLL中引入偏移量，视频数据可以通过 SRC。

2. 发明授权

US07474724B1 Method and system for video-synchronous audio clock generation from an asynchronously sampled video signal 有权
标题翻译：用于从异步采样的视频信号产生视频同步音频时钟的方法和系统
公开(公告)号：US07474724B1
公开(公告)日：2009-01-06
申请号：US11082347
申请日：2005-03-17
申请人： Daniel Gudmunson , John Melanson , Rahul Singh , Ahsan Chowdhury
发明人： Daniel Gudmunson , John Melanson , Rahul Singh , Ahsan Chowdhury
IPC分类号： H03D3/24
CPC分类号： H03L7/1974 , H03L7/08 , H03L7/0805 , H03L2207/50 , H04N5/12 , H04N5/213 , H04N5/765 , H04N5/85 , H04N7/0132 , H04N9/8042 , H04N9/896 , H04N21/4325 , H04N21/44004
摘要： A method and system for video-synchronous audio clock generation from an asynchronously sampled video signal provides a mechanism for maintaining synchronization of audio sampling in digital video-audio systems. A ratio between the sampling clock frequency and an audio reference frequency clock is computed via an all digital phase-lock loop (ADPLL) and an audio clock is generated from the ratio by another PLL or a number to clock converter. In systems where a sampling clock to source video clock ratio has been computed for recovering a video signal, the audio ratio can be computed directly from the video ratio.
摘要翻译：用于从异步采样的视频信号产生视频同步音频时钟的方法和系统提供了一种用于维持数字视频 - 音频系统中音频采样同步的机制。通过全数字锁相环（ADPLL）计算采样时钟频率和音频参考频率时钟之间的比例，并且通过另一PLL或数字到时钟转换器从该比率产生音频时钟。在已经计算了用于恢复视频信号的源视频时钟比的采样时钟的系统中，可以从视频比率直接计算音频比。

3. 发明授权

US07158045B1 Method and apparatus for maintaining an ideal frequency ratio between numerically-controlled frequency sources 有权
标题翻译：用于维持数控频率源之间的理想频率比的方法和装置
公开(公告)号：US07158045B1
公开(公告)日：2007-01-02
申请号：US11088446
申请日：2005-03-24
申请人： Daniel Gudmunson , John Melanson , Rahul Singh , Ahsan Chowdhury
发明人： Daniel Gudmunson , John Melanson , Rahul Singh , Ahsan Chowdhury
IPC分类号： H04L7/00
CPC分类号： H03L7/0994 , H03L7/07 , H03L7/0805 , H03L7/197
摘要： A method and apparatus for maintaining an ideal frequency ratio between numerically-controlled frequency sources provides a mechanism for maintaining coherence between multiple synchronization references where a known ideal rational relationship between the sources is known. Multiple numerically controlled oscillators (NCOs) generate the multiple synchronization references, which may be clock signals or numeric phase representations and the outputs of the NCOs are compared with a ratiometric frequency comparator that determines whether there is an error in the ratio between the NCO outputs. The frequency of one of the NCOs is then adjusted with a frequency correction factor provided by the ratiometric frequency comparator. The NCO inputs can represent ratios of the synchronization reference frequencies to a fixed reference clock and the NCOs clocked by the fixed reference clock.
摘要翻译：用于在数控频率源之间保持理想频率比的方法和装置提供了一种维持多个同步参考之间的相干性的机制，其中已知的源之间的理想的理性关系是已知的。多个数控振荡器（NCO）产生多个同步参考，其可以是时钟信号或数字相位表示，并且将NCO的输出与比较率频率比较器进行比较，其确定NCO输出之间的比率是否存在误差。然后用比例式频率比较器提供的频率校正因子来调整NCO之一的频率。 NCO输入可以表示同步参考频率与固定参考时钟的比率和由固定参考时钟计时的NCO。

4. 发明申请

US20060077296A1 Inverse tracking over two different clock domains 失效
标题翻译：反向跟踪两个不同的时钟域
公开(公告)号：US20060077296A1
公开(公告)日：2006-04-13
申请号：US10964556
申请日：2004-10-13
申请人： Daniel Gudmundson , John Melanson , Rahul Singh , Ahsan Chowdhury
发明人： Daniel Gudmundson , John Melanson , Rahul Singh , Ahsan Chowdhury
IPC分类号： H04N11/00
CPC分类号： H03L7/06 , H03L7/0991 , H03L2207/50 , H04L7/005 , H04L7/0331 , H04N5/126
摘要： A video decoder in which the video source clock is generated entirely in the digital domain is disclosed herein. By creating a virtual version of the source clock in a numeric oscillator, the amount of noise in the system is substantially reduced. Furthermore, by transferring the digitized video signal, sampled with an asynchronous crystal clock, into the source clock domain, the accuracy of the brightness (amplitude) and color (phase) information can be greatly enhanced.
摘要翻译：本文公开了视频源时钟完全在数字域中生成的视频解码器。通过在数字振荡器中创建源时钟的虚拟版本，系统中的噪声量显着降低。此外，通过将用异步晶体时钟采样的数字化视频信号传送到源时钟域，可以大大提高亮度（幅度）和颜色（相位）信息的精度。

5. 发明申请

US20060078054A1 Method and apparatus to improve decoding of composite video signals 有权
标题翻译：改善复合视频信号解码的方法和装置
公开(公告)号：US20060078054A1
公开(公告)日：2006-04-13
申请号：US10964547
申请日：2004-10-13
申请人： Daniel Gudmundson , John Melanson , Rahul Singh , James Antone , Ahsan Chowdhury , Krishnan Subramoniam
发明人： Daniel Gudmundson , John Melanson , Rahul Singh , James Antone , Ahsan Chowdhury , Krishnan Subramoniam
IPC分类号： H04N11/02 , H04N11/04 , H04N7/12 , H04B1/66
CPC分类号： H04N5/4401 , H04N5/602 , H04N5/76 , H04N5/781 , H04N9/8042 , H04N11/20 , H04N21/4147 , H04N21/4305
摘要： Video decoder systems in which both the analog-to-digital converter and the composite decoder are driven by the stable sample clock, such as a crystal source. The outputs of the composite decoder are provided to a source rate converter, having an output that is provided to a digital output formatter. The digital output formatter is driven by the output clock, which may be locked to the source clock if desired. The output clock is developed by a clock generator which may be one of several different types, including a fractional N synthesizer, a direct digital synthesizer or a puncture clock.
摘要翻译：视频解码器系统，其中模数转换器和复合解码器均由诸如晶体源的稳定采样时钟驱动。复合解码器的输出被提供给源速率转换器，其具有提供给数字输出格式器的输出。数字输出格式化器由输出时钟驱动，如果需要，可以将其锁定到源时钟。输出时钟由时钟发生器开发，时钟发生器可以是几种不同类型之一，包括分数N个合成器，直接数字合成器或穿孔时钟。

6. 发明授权

US07154562B1 Methods and circuits for implementing programmable gamma correction 有权
标题翻译：实现可编程伽玛校正的方法和电路
公开(公告)号：US07154562B1
公开(公告)日：2006-12-26
申请号：US10685128
申请日：2003-10-14
申请人： Ahsan Chowdhury , Anand Venkitachalam , John Melanson
发明人： Ahsan Chowdhury , Anand Venkitachalam , John Melanson
IPC分类号： H04N5/202 , H04N9/69
CPC分类号： H04N5/202
摘要： A method of gamma correction includes selecting lower and upper reference curves corresponding to selected reference gamma values. A gamma correction curve is generated from a corresponding gamma correction value and cross-correlated with the upper and lower reference curves to generate a corresponding set of cross-correlation factors. The set of cross-correlation factors are stored and indexed to the corresponding gamma value. An input value is received for gamma correction with the corresponding gamma value. Data from the upper and lower reference curves indexed by the input value are then operated one with the cross-correlation factors to generate a gamma corrected output value.
摘要翻译：伽马校正的方法包括选择对应于所选参考伽马值的下参考曲线和上参考曲线。从相应的伽马校正值产生伽马校正曲线，并与上参考曲线和下参考曲线交叉相关，以产生相应的一组互相关因子。互相关因子的集合被存储并被索引到相应的伽马值。接收用于具有相应伽马值的伽马校正的输入值。然后，通过输入值索引的来自上下参考曲线的数据与互相关因子一起运算，以产生伽马校正输出值。

7. 发明申请

US20070263888A1 METHOD AND SYSTEM FOR SURROUND SOUND BEAM-FORMING USING VERTICALLY DISPLACED DRIVERS 有权
标题翻译：使用垂直位移驱动器的环形波束形成的方法和系统
公开(公告)号：US20070263888A1
公开(公告)日：2007-11-15
申请号：US11421381
申请日：2006-05-31
申请人： John Melanson
发明人： John Melanson
IPC分类号： H04R5/02
CPC分类号： H04S3/00 , H04R1/403 , H04R3/12 , H04R2201/401 , H04R2205/022 , H04R2430/20
摘要： A method and system for surround sound beam-forming using vertically displaced drivers provides a low cost alternative to present external surround array systems. A pair of vertically displaced speaker drivers is supplied with surround and main channel information in a controlled phase relationship with respect to each driver such that the surround channel information is propagated in a directivity pattern substantially differing from that of the main channel information. The main channel information is generally directed at a listening area, while the surround channel information is directed away from the listening area and is substantially attenuated in the direction of the listening area, so that the surround channel information is heard as a diffuse reflected field. An electronic network provides for control of the surround channel phase relationship and combining of main and surround signals for providing inputs to individual power amplifiers for each driver.
摘要翻译：使用垂直移位的驱动器的环绕声波束形成的方法和系统为现在的外部环绕阵列系统提供了低成本的替代方案。一对垂直移位的扬声器驱动器以相对于每个驱动器的受控相位关系提供环绕声道和主声道信息，使得环绕声道信息以与主声道信息的方向性图案基本不同的方向性图案传播。主声道信息通常指向收听区域，而环绕声道信息被指向远离聆听区域并且在聆听区域的方向上基本衰减，使得环绕声道信息被作为漫反射场被听到。电子网络提供环绕声道相位关系的控制，以及用于向每个驱动器的各个功率放大器提供输入的主信号和环绕信号的组合。

8. 发明申请

US20060232331A1 Segmented chopping amplifier 有权
公开(公告)号：US20060232331A1
公开(公告)日：2006-10-19
申请号：US11455592
申请日：2006-06-19
申请人： Karl Thompson , John Melanson , Chung-Kai Chow , Ammisetti Prasad
发明人： Karl Thompson , John Melanson , Chung-Kai Chow , Ammisetti Prasad
IPC分类号： H03F1/02
CPC分类号： H03F3/211 , H03F1/02 , H03F1/26 , H03F3/217 , H03F3/38 , H03F2200/331
摘要： A chopping amplifier and method for chopping an input signal are disclosed. The chopping amplifier and method utilize at least two chopping amplifier stages. A chopping operation of an input signal is segmented across two or more chopping amplifier stages, and the two or more chopping amplifier stages are responsive to a master controller. Chop clock signals of the chopping amplifier stages are staggered so that they have non-overlapping periods and at least one of the chopping amplifier stages is not operating in an open loop at any given time. The non-overlapping periods are periodic so that a master chop clock of the master controller can be operated at a lower chop clock frequency. For every doubling of N number of chopping amplifier stages, magnitudes of chopping artifacts and aliased components are each respectively reduced by 3 dB.

9. 发明申请

US20060114031A1 Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector 有权
$Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector$
公开(公告)号：US20060114031A1
公开(公告)日：2006-06-01
申请号：US11331638
申请日：2006-01-13
申请人： John Melanson
发明人： John Melanson
IPC分类号： H03D13/00
CPC分类号： H03K23/68 , H03K23/546
摘要： A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.

10. 发明授权

US07015853B1 Data converter with reduced differential nonlinearity 有权
标题翻译：数据转换器具有降低的差分非线性
公开(公告)号：US07015853B1
公开(公告)日：2006-03-21
申请号：US11076790
申请日：2005-03-09
申请人： Clinton R. Wolff , John Melanson
发明人： Clinton R. Wolff , John Melanson
IPC分类号： H03M1/38
CPC分类号： H03M1/0641 , H03M1/468
摘要： Methods and apparatus are provided for reducing nonlinearities in an analog-to-digital signal converter. An analog pseudo-random noise sample is added to an analog input sample and the combined sample is converted into a digital representation. A pseudo-random digital sample corresponding to the analog noise sample is subtracted from the converted digital representation. Preferably, multiple analog noise samples are added to the analog input sample, converted and corresponding digital noise samples subtracted from the converted digital representation. The multiple digital representations are then averaged, thereby nullifying differential nonlinearities in various portions of the transfer characteristics curve of the signal converter and reducing the effects of the DNL.
摘要翻译：提供了用于降低模拟 - 数字信号转换器中的非线性的方法和装置。将模拟伪随机噪声样本添加到模拟输入样本，并将组合的样本转换为数字表示。从转换的数字表示中减去对应于模拟噪声样本的伪随机数字样本。优选地，将多个模拟噪声样本添加到模拟输入样本，从转换的数字表示中减去转换和相应的数字噪声样本。然后对多个数字表示进行平均，从而使信号转换器的传输特性曲线的各个部分中的微分非线性无效，并减少DNL的影响。

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