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1. 发明授权

US08900962B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08900962B2
公开(公告)日：2014-12-02
申请号：US13052309
申请日：2011-03-21
申请人： Daisuke Yamashita , Etsuo Hamada , Hideki Nozaki , Hironobu Shibata
发明人： Daisuke Yamashita , Etsuo Hamada , Hideki Nozaki , Hironobu Shibata
IPC分类号： H01L21/331 , H01L29/66 , H01L21/268 , H01L29/739 , H01L29/08 , H01L21/266 , H01L21/265
CPC分类号： H01L29/66333 , H01L21/26513 , H01L21/266 , H01L21/268 , H01L29/0834 , H01L29/7395
摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a base region and an emitter region in a front surface of a semiconductor layer. The method can include forming a first impurity implantation region by implanting first impurity of a first conductivity type into a back surface of the semiconductor layer. The method can include selectively forming a second impurity implantation region by selectively implanting second impurity of a second conductivity type into the first impurity implantation region. In addition, the method can include irradiating the first impurity implantation region and the second impurity implantation region with laser light. A peak of impurity concentration profile in a depth direction of at least one of the first impurity implantation region and the second impurity implantation region before irradiation with the laser light is adjusted to a depth of 0.05 μm or more and 0.3 μm or less from the back surface of the semiconductor layer.
摘要翻译：根据一个实施例，公开了一种用于制造半导体器件的方法。该方法可以包括在半导体层的前表面中形成基极区域和发射极区域。该方法可以包括通过将第一导电类型的第一杂质注入半导体层的后表面来形成第一杂质注入区。该方法可以包括通过将第二导电类型的第二杂质选择性地注入到第一杂质注入区域中来选择性地形成第二杂质注入区域。此外，该方法可以包括用激光照射第一杂质注入区域和第二杂质注入区域。将激光照射前的第一杂质注入区域和第二杂质注入区域中的至少一个的深度方向的杂质浓度分布的峰值从背面调整为0.05μm以上且0.3μm以下的深度半导体层的表面。

2. 发明申请

US20110250728A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110250728A1
公开(公告)日：2011-10-13
申请号：US13052309
申请日：2011-03-21
申请人： Daisuke Yamashita , Etsuo Hamada , Hideki Nozaki , Hironobu Shibata
发明人： Daisuke Yamashita , Etsuo Hamada , Hideki Nozaki , Hironobu Shibata
IPC分类号： H01L21/331
CPC分类号： H01L29/66333 , H01L21/26513 , H01L21/266 , H01L21/268 , H01L29/0834 , H01L29/7395
摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a base region and an emitter region in a front surface of a semiconductor layer. The method can include forming a first impurity implantation region by implanting first impurity of a first conductivity type into a back surface of the semiconductor layer. The method can include selectively forming a second impurity implantation region by selectively implanting second impurity of a second conductivity type into the first impurity implantation region. In addition, the method can include irradiating the first impurity implantation region and the second impurity implantation region with laser light. A peak of impurity concentration profile in a depth direction of at least one of the first impurity implantation region and the second impurity implantation region before irradiation with the laser light is adjusted to a depth of 0.05 μm or more and 0.3 μm or less from the back surface of the semiconductor layer.
摘要翻译：根据一个实施例，公开了一种用于制造半导体器件的方法。该方法可以包括在半导体层的前表面中形成基极区域和发射极区域。该方法可以包括通过将第一导电类型的第一杂质注入半导体层的后表面来形成第一杂质注入区。该方法可以包括通过将第二导电类型的第二杂质选择性地注入到第一杂质注入区域中来选择性地形成第二杂质注入区域。此外，该方法可以包括用激光照射第一杂质注入区域和第二杂质注入区域。将激光照射前的第一杂质注入区域和第二杂质注入区域中的至少一个的深度方向的杂质浓度分布的峰值从背面调整为0.05μm以上且0.3μm以下的深度半导体层的表面。

3. 发明申请

US20100203688A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100203688A1
公开(公告)日：2010-08-12
申请号：US12759457
申请日：2010-04-13
申请人： Motoshige Kobayashi , Hideki Nozaki , Masanobu Tsuchitani
发明人： Motoshige Kobayashi , Hideki Nozaki , Masanobu Tsuchitani
IPC分类号： H01L21/336 , H01L21/78
CPC分类号： H01L29/7395 , H01L24/93 , H01L29/0834 , H01L29/0847 , H01L29/7397 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer having a first major surface, a second major surface provided on opposite side of the first major surface, and a channel formation region provided in a surface portion on the first major surface side; a first main electrode provided inside a dicing street on the first major surface of the semiconductor layer; a second main electrode provided inside a dicing street on the second major surface of the semiconductor layer; and a control electrode opposed to the channel formation region across an insulating film.
摘要翻译：半导体器件包括：具有第一主表面的半导体层，设置在第一主表面的相对侧上的第二主表面和设置在第一主表面侧的表面部分中的沟道形成区域; 设置在半导体层的第一主表面上的切割街道内的第一主电极; 设置在半导体层的第二主表面上的切割街道内的第二主电极; 以及与跨越绝缘膜的沟道形成区域相对的控制电极。

4. 发明申请

US20100048000A1 METHOD OF MANUFACTURING SEMICONDUCTOR CHIPS 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100048000A1
公开(公告)日：2010-02-25
申请号：US12545573
申请日：2009-08-21
申请人： Motoshige Kobayashi , Hideki Nozaki
发明人： Motoshige Kobayashi , Hideki Nozaki
IPC分类号： H01L21/304
CPC分类号： H01L21/6835 , H01L21/6836 , H01L29/0657 , H01L2221/68327 , H01L2221/68336 , H01L2221/6834
摘要： A semiconductor wafer is prepared. The wafer has a first and a second surface opposite to each other, and has a recess portion and a rim portion. The semiconductor wafer has semiconductor elements formed on the first surface. The rim portion surrounds the recess portion. The recess portion and the rim portion are composed of the first and second surfaces. The recess portion is formed so as to recede toward the first surface. A tape is adhered to the second surface of the semiconductor wafer. At least the recess portion of the semiconductor wafer is placed on a stage. The tape is sandwiched between the recess portion and the stage. Laser beam is irradiated to the recess portion from the side of the first surface and along predetermined dicing lines. The recess portion is cut off to divide the semiconductor wafer into chips.
摘要翻译：准备半导体晶片。晶片具有彼此相对的第一和第二表面，并且具有凹部和边缘部。半导体晶片具有形成在第一表面上的半导体元件。边缘部分围绕凹部。凹部和边缘部由第一表面和第二表面构成。凹部形成为朝向第一面后退。胶带粘附到半导体晶片的第二表面。至少将半导体晶片的凹部放置在台上。带被夹在凹部和台之间。激光束从第一表面的一侧沿着预定的切割线照射到凹部。将凹部切断，将半导体晶片分割成芯片。

5. 发明授权

US06562705B1 Method and apparatus for manufacturing semiconductor element 失效
标题翻译：用于制造半导体元件的方法和装置
公开(公告)号：US06562705B1
公开(公告)日：2003-05-13
申请号：US09696167
申请日：2000-10-26
申请人： Takashi Obara , Hideki Nozaki , Motoshige Kobayashi
发明人： Takashi Obara , Hideki Nozaki , Motoshige Kobayashi
IPC分类号： H01L2126
CPC分类号： H01L29/66333 , H01L21/26513 , H01L21/268 , H01L21/28512
摘要： A laser heating apparatus for forming an electrode on one surface of an Si chip provided on an Si wafer, thereby producing a semiconductor element, comprises a high vacuum chamber having a light transmission window, an XY table contained in the high vacuum chamber for mounting the Si wafer thereon, heater contained in the high vacuum chamber for heating and evaporating an impurity in a solid state, and laser beam applying means for applying a laser beam to the Si chip placed on the XY table from the outside of the high vacuum chamber through the light transmission window, thereby implanting the impurity into the Si in chip and activating the implanted impurity.
摘要翻译：一种激光加热装置，用于在Si晶片上设置的Si芯片的一个表面上形成电极，从而制造半导体元件，包括具有透光窗的高真空室，包含在高真空室中的XY台，用于安装 Si晶片，包含在用于加热和蒸发固态杂质的高真空室中的加热器，以及激光束施加装置，用于从高真空室的外部向位于XY工作台上的Si芯片施加激光束，激光束施加装置通过透光窗，从而将杂质注入芯片中的Si并激活注入的杂质。

6. 发明授权

US6121635A Semiconductor light-emitting element having transparent electrode and current blocking layer, and semiconductor light-emitting including the same 失效
标题翻译：具有透明电极和电流阻挡层的半导体发光元件和包含该半导体发光元件的半导体发光元件
公开(公告)号：US6121635A
公开(公告)日：2000-09-19
申请号：US60549
申请日：1998-04-15
申请人： Yukio Watanabe , Ryo Saeki , Hideki Nozaki
发明人： Yukio Watanabe , Ryo Saeki , Hideki Nozaki
IPC分类号： H01L33/14 , H01L33/30 , H01L33/38 , H01L33/42 , H01L33/56 , H01L33/60 , H01L33/62 , H01L33/00
CPC分类号： H01L33/42 , H01L33/145 , H01L33/30 , H01L2224/32245 , H01L2224/32257 , H01L2224/48247 , H01L2224/48463 , H01L2224/73265 , H01L2924/181
摘要： A current blocking layer (7) formed immediately below a transparent electrode (9) is formed of a semiconductor layer containing Al, and a bandgap equal to or longer than the emission wavelength. Since the current blocking layer (7) is formed of such semiconductor layer, an oxide film forms on or near the surface of the current blocking layer (7) in a process of forming the transparent electrode (9) such as an ITO film containing oxygen, and the current blocking layer functions effectively. The diameter of a bonding electrode (20) is set to be smaller than that of the current blocking layer (7), thus effectively outputting the light emitted. Furthermore, the oxidized current blocking layer can have a high breakdown voltage and, hence, can be formed to have a small thickness, thus improving step coverage upon forming the transparent electrode on the current blocking layer. By inserting a thin Zn layer (8) between the transparent electrode (9) and an ohmic layer (6), the adhesion therebetween can be improved.
摘要翻译：由透明电极（9）正下方形成的电流阻挡层（7）由包含Al的半导体层和等于或大于发射波长的带隙形成。由于电流阻挡层（7）由这种半导体层形成，所以在形成透明电极（9）的过程中，在电流阻挡层（7）的表面上或附近形成氧化膜，例如含有氧的ITO膜，并且当前的阻塞层有效地起作用。接合电极（20）的直径被设定为小于电流阻挡层（7）的直径，从而有效地输出发射的光。此外，氧化电流阻挡层可以具有高的击穿电压，因此可以形成为具有小的厚度，从而在电流阻挡层上形成透明电极时提高了阶梯覆盖。通过在透明电极（9）和欧姆层（6）之间插入薄Zn层（8），可以提高它们之间的粘合性。

7. 发明授权

US07906416B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07906416B2
公开(公告)日：2011-03-15
申请号：US11871525
申请日：2007-10-12
申请人： Masanobu Tsuchitani , Hideki Nozaki , Motoshige Kobayashi
发明人： Masanobu Tsuchitani , Hideki Nozaki , Motoshige Kobayashi
IPC分类号： H01L21/00
CPC分类号： H01L21/268 , H01L29/0834 , H01L29/66333 , H01L29/66348 , H01L29/7395 , H01L29/7397
摘要： A method for manufacturing a semiconductor device from a semiconductor wafer having a first major surface, a recess provided inside a periphery on opposite side of the first major surface and surrounded by the periphery, and a second major surface provided at bottom of the recess is provided. The method comprises: fitting into the recess a doping mask having selectively formed openings to selectively cover the second major surface with the doping mask; and selectively introducing dopant into the second major surface.
摘要翻译：一种从半导体晶片制造半导体器件的方法，该半导体晶片具有第一主表面，设置在第一主表面的相对侧的周边内周围并被周边包围的凹部，以及设置在凹部底部的第二主表面。该方法包括：将具有选择性地形成的开口的掺杂掩模装入凹槽中，以用掺杂掩模选择性地覆盖第二主表面; 并选择性地将掺杂剂引入第二主表面。

8. 发明申请

US20070210350A1 POWER SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND METHOD FOR DRIVING SAME 有权
标题翻译：功率半导体器件，其制造方法及其驱动方法
公开(公告)号：US20070210350A1
公开(公告)日：2007-09-13
申请号：US11682670
申请日：2007-03-06
申请人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
发明人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
IPC分类号： H01L29/80
CPC分类号： H01L29/7397 , H01L23/4824 , H01L29/0619 , H01L29/0696 , H01L29/41775 , H01L29/4236 , H01L29/66348 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.
摘要翻译：功率半导体器件包括：半导体层，具有沿条形配置沿着第一方向延伸的沟槽; 掩埋在所述沟槽中的用于控制在所述半导体层中流动的电流的栅电极; 以及由具有比栅极电极更高的导电性的材料制成的栅极插塞，栅极插塞具有带状结构，并沿第一方向连接到栅电极。半导体层包括：第一导电类型的第一半导体层; 第二导电类型的第二半导体层，部分地设置在第一半导体层的上表面上; 第一导电类型的第三半导体层部分地设置在第二半导体层上; 以及设置在第一半导体层的下表面上的第二导电类型的第四半导体层。

9. 发明申请

US20060095428A1 Method and apparatus for displaying system management information, computer product for the same, and operation management system 有权
标题翻译：用于显示系统管理信息，计算机产品和操作管理系统的方法和装置
公开(公告)号：US20060095428A1
公开(公告)日：2006-05-04
申请号：US11045871
申请日：2005-01-28
申请人： Hideo Sugimori , Masashi Ogawa , Hideki Nozaki , Seiya Shindo , Hiroshi Yazawa , Shinichi Doi , Taisuke Aizawa , Ken Takahashi , Gaku Sakurai
发明人： Hideo Sugimori , Masashi Ogawa , Hideki Nozaki , Seiya Shindo , Hiroshi Yazawa , Shinichi Doi , Taisuke Aizawa , Ken Takahashi , Gaku Sakurai
IPC分类号： G06F17/30
CPC分类号： G06F11/324 , Y10S707/99936 , Y10S707/99945
摘要： An apparatus for displaying system management information includes a combination storing unit that stores display pattern information that is obtained by combining, in subjective basis, system management information provided by a plurality of system management units; and a combination display unit that combines the system management information based on the display pattern stored in the combination storing unit, and displays the system management information combined.
摘要翻译：一种用于显示系统管理信息的装置，包括组合存储单元，其存储通过主观地组合由多个系统管理单元提供的系统管理信息而获得的显示模式信息; 以及组合显示单元，其组合基于存储在组合存储单元中的显示模式的系统管理信息，并显示组合的系统管理信息。

10. 发明授权

US06649981B2 High breakdown voltage semiconductor device 有权
标题翻译：高击穿电压半导体器件
公开(公告)号：US06649981B2
公开(公告)日：2003-11-18
申请号：US10107405
申请日：2002-03-28
申请人： Motoshige Kobayashi , Hideki Nozaki
发明人： Motoshige Kobayashi , Hideki Nozaki
IPC分类号： H01L2362
CPC分类号： H01L29/66333 , H01L29/36 , H01L29/7395
摘要： A semiconductor device comprises a first base layer for providing a PT-IGBT or IEGT structure, which includes a buffer layer and a collector layer provided in the buffer layer. A first activation rate, defined by an activated first conductivity type impurity density [cm−2] in the buffer layer due to SR analysis/a first conductivity type impurity density [cm−2] in the buffer layer due to SIMS analysis is given by 25% or more, and a second activation rate, defined by an activated second conductivity type impurity density [cm−2] in the collector layer due to SR analysis/a second conductivity type impurity density [cm−2] in the collector layer duet to SIMS analysis is given by more than 0% and 10% or less.
摘要翻译：半导体器件包括用于提供PT-IGBT或IEGT结构的第一基极层，其包括设置在缓冲层中的缓冲层和集电极层。由缓冲层中的SR分析/第一导电型杂质浓度[cm -2]在缓冲层中由于SIMS而由活化的第一导电类型杂质密度[cm -2]限定的第一活化速率分析为25％以上，由于SR分析/第二导电型杂质密度[cm -1]，在集电体层中由活化的第二导电型杂质浓度[cm -2]限定的第二活化率， 2>]在集电极二极管到SIMS分析中给出了超过0％和10％以下。

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