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1. 发明申请

US20080296611A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080296611A1
公开(公告)日：2008-12-04
申请号：US11871541
申请日：2007-10-12
申请人： Motoshige Kobayashi , Hideki Nozaki , Masanobu Tsuchitani
发明人： Motoshige Kobayashi , Hideki Nozaki , Masanobu Tsuchitani
IPC分类号： H01L29/772 , H01L21/332
CPC分类号： H01L29/7395 , H01L24/93 , H01L29/0834 , H01L29/0847 , H01L29/7397 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer having a first major surface, a second major surface provided on opposite side of the first major surface, and a channel formation region provided in a surface portion on the first major surface side; a first main electrode provided inside a dicing street on the first major surface of the semiconductor layer; a second main electrode provided inside a dicing street on the second major surface of the semiconductor layer; and a control electrode opposed to the channel formation region across an insulating film.
摘要翻译：半导体器件包括：具有第一主表面的半导体层，设置在第一主表面的相对侧上的第二主表面和设置在第一主表面侧的表面部分中的沟道形成区域; 设置在半导体层的第一主表面上的切割街道内的第一主电极; 设置在半导体层的第二主表面上的切割街道内的第二主电极; 以及与跨越绝缘膜的沟道形成区域相对的控制电极。

2. 发明申请

US20100203688A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100203688A1
公开(公告)日：2010-08-12
申请号：US12759457
申请日：2010-04-13
申请人： Motoshige Kobayashi , Hideki Nozaki , Masanobu Tsuchitani
发明人： Motoshige Kobayashi , Hideki Nozaki , Masanobu Tsuchitani
IPC分类号： H01L21/336 , H01L21/78
CPC分类号： H01L29/7395 , H01L24/93 , H01L29/0834 , H01L29/0847 , H01L29/7397 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer having a first major surface, a second major surface provided on opposite side of the first major surface, and a channel formation region provided in a surface portion on the first major surface side; a first main electrode provided inside a dicing street on the first major surface of the semiconductor layer; a second main electrode provided inside a dicing street on the second major surface of the semiconductor layer; and a control electrode opposed to the channel formation region across an insulating film.
摘要翻译：半导体器件包括：具有第一主表面的半导体层，设置在第一主表面的相对侧上的第二主表面和设置在第一主表面侧的表面部分中的沟道形成区域; 设置在半导体层的第一主表面上的切割街道内的第一主电极; 设置在半导体层的第二主表面上的切割街道内的第二主电极; 以及与跨越绝缘膜的沟道形成区域相对的控制电极。

3. 发明授权

US07906416B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07906416B2
公开(公告)日：2011-03-15
申请号：US11871525
申请日：2007-10-12
申请人： Masanobu Tsuchitani , Hideki Nozaki , Motoshige Kobayashi
发明人： Masanobu Tsuchitani , Hideki Nozaki , Motoshige Kobayashi
IPC分类号： H01L21/00
CPC分类号： H01L21/268 , H01L29/0834 , H01L29/66333 , H01L29/66348 , H01L29/7395 , H01L29/7397
摘要： A method for manufacturing a semiconductor device from a semiconductor wafer having a first major surface, a recess provided inside a periphery on opposite side of the first major surface and surrounded by the periphery, and a second major surface provided at bottom of the recess is provided. The method comprises: fitting into the recess a doping mask having selectively formed openings to selectively cover the second major surface with the doping mask; and selectively introducing dopant into the second major surface.
摘要翻译：一种从半导体晶片制造半导体器件的方法，该半导体晶片具有第一主表面，设置在第一主表面的相对侧的周边内周围并被周边包围的凹部，以及设置在凹部底部的第二主表面。该方法包括：将具有选择性地形成的开口的掺杂掩模装入凹槽中，以用掺杂掩模选择性地覆盖第二主表面; 并选择性地将掺杂剂引入第二主表面。

4. 发明授权

US06524894B1 Semiconductor device for use in power-switching device and method of manufacturing the same 有权
标题翻译：用于电力开关装置的半导体装置及其制造方法
公开(公告)号：US06524894B1
公开(公告)日：2003-02-25
申请号：US09783303
申请日：2001-02-15
申请人： Hideki Nozaki , Yoshiro Baba , Motoshige Kobayashi
发明人： Hideki Nozaki , Yoshiro Baba , Motoshige Kobayashi
IPC分类号： H01L21332
CPC分类号： H01L29/0834 , H01L29/7395 , H01L29/7397
摘要： An N+ buffer layer formed on the underside of an N− layer includes an inactive region having incompletely activated ions and an active region having highly activated ions. The carrier concentration of the active region is higher than that of the inactive region. In the inactive region, the electrical activation rate X of the ions is expressed as 1%≦X≦30%. It is thus possible to achieve a PT structure using a Raw wafer, which reduces manufacturing costs and suppresses power consumption.
摘要翻译：形成在N-层的下侧上的N +缓冲层包括具有不完全活化的离子的非活性区域和具有高活性离子的活性区域。有源区的载流子浓度高于非活性区的载流子浓度。在非活性区域中，离子的电活化速率X表示为1％<= X <= 30％。因此，可以实现使用原始晶片的PT结构，这降低了制造成本并抑制了功耗。

5. 发明授权

US08148240B2 Method of manufacturing semiconductor chips 有权
标题翻译：制造半导体芯片的方法
公开(公告)号：US08148240B2
公开(公告)日：2012-04-03
申请号：US12545573
申请日：2009-08-21
申请人： Motoshige Kobayashi , Hideki Nozaki
发明人： Motoshige Kobayashi , Hideki Nozaki
IPC分类号： H01L21/304
CPC分类号： H01L21/6835 , H01L21/6836 , H01L29/0657 , H01L2221/68327 , H01L2221/68336 , H01L2221/6834
摘要： A semiconductor wafer is prepared. The wafer has a first and a second surface opposite to each other, and has a recess portion and a rim portion. The semiconductor wafer has semiconductor elements formed on the first surface. The rim portion surrounds the recess portion. The recess portion and the rim portion are composed of the first and second surfaces. The recess portion is formed so as to recede toward the first surface. A tape is adhered to the second surface of the semiconductor wafer. At least the recess portion of the semiconductor wafer is placed on a stage. The tape is sandwiched between the recess portion and the stage. Laser beam is irradiated to the recess portion from the side of the first surface and along predetermined dicing lines. The recess portion is cut off to divide the semiconductor wafer into chips.
摘要翻译：准备半导体晶片。晶片具有彼此相对的第一和第二表面，并且具有凹部和边缘部。半导体晶片具有形成在第一表面上的半导体元件。边缘部分围绕凹部。凹部和边缘部由第一表面和第二表面构成。凹部形成为朝向第一面后退。胶带粘附到半导体晶片的第二表面。至少将半导体晶片的凹部放置在台上。带被夹在凹部和台之间。激光束从第一表面的一侧沿着预定的切割线照射到凹部。将凹部切断，将半导体晶片分割成芯片。

6. 发明申请

US20100048000A1 METHOD OF MANUFACTURING SEMICONDUCTOR CHIPS 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100048000A1
公开(公告)日：2010-02-25
申请号：US12545573
申请日：2009-08-21
申请人： Motoshige Kobayashi , Hideki Nozaki
发明人： Motoshige Kobayashi , Hideki Nozaki
IPC分类号： H01L21/304
CPC分类号： H01L21/6835 , H01L21/6836 , H01L29/0657 , H01L2221/68327 , H01L2221/68336 , H01L2221/6834
摘要： A semiconductor wafer is prepared. The wafer has a first and a second surface opposite to each other, and has a recess portion and a rim portion. The semiconductor wafer has semiconductor elements formed on the first surface. The rim portion surrounds the recess portion. The recess portion and the rim portion are composed of the first and second surfaces. The recess portion is formed so as to recede toward the first surface. A tape is adhered to the second surface of the semiconductor wafer. At least the recess portion of the semiconductor wafer is placed on a stage. The tape is sandwiched between the recess portion and the stage. Laser beam is irradiated to the recess portion from the side of the first surface and along predetermined dicing lines. The recess portion is cut off to divide the semiconductor wafer into chips.
摘要翻译：准备半导体晶片。晶片具有彼此相对的第一和第二表面，并且具有凹部和边缘部。半导体晶片具有形成在第一表面上的半导体元件。边缘部分围绕凹部。凹部和边缘部由第一表面和第二表面构成。凹部形成为朝向第一面后退。胶带粘附到半导体晶片的第二表面。至少将半导体晶片的凹部放置在台上。带被夹在凹部和台之间。激光束从第一表面的一侧沿着预定的切割线照射到凹部。将凹部切断，将半导体晶片分割成芯片。

7. 发明授权

US06562705B1 Method and apparatus for manufacturing semiconductor element 失效
标题翻译：用于制造半导体元件的方法和装置
公开(公告)号：US06562705B1
公开(公告)日：2003-05-13
申请号：US09696167
申请日：2000-10-26
申请人： Takashi Obara , Hideki Nozaki , Motoshige Kobayashi
发明人： Takashi Obara , Hideki Nozaki , Motoshige Kobayashi
IPC分类号： H01L2126
CPC分类号： H01L29/66333 , H01L21/26513 , H01L21/268 , H01L21/28512
摘要： A laser heating apparatus for forming an electrode on one surface of an Si chip provided on an Si wafer, thereby producing a semiconductor element, comprises a high vacuum chamber having a light transmission window, an XY table contained in the high vacuum chamber for mounting the Si wafer thereon, heater contained in the high vacuum chamber for heating and evaporating an impurity in a solid state, and laser beam applying means for applying a laser beam to the Si chip placed on the XY table from the outside of the high vacuum chamber through the light transmission window, thereby implanting the impurity into the Si in chip and activating the implanted impurity.
摘要翻译：一种激光加热装置，用于在Si晶片上设置的Si芯片的一个表面上形成电极，从而制造半导体元件，包括具有透光窗的高真空室，包含在高真空室中的XY台，用于安装 Si晶片，包含在用于加热和蒸发固态杂质的高真空室中的加热器，以及激光束施加装置，用于从高真空室的外部向位于XY工作台上的Si芯片施加激光束，激光束施加装置通过透光窗，从而将杂质注入芯片中的Si并激活注入的杂质。

8. 发明授权

US06649981B2 High breakdown voltage semiconductor device 有权
标题翻译：高击穿电压半导体器件
公开(公告)号：US06649981B2
公开(公告)日：2003-11-18
申请号：US10107405
申请日：2002-03-28
申请人： Motoshige Kobayashi , Hideki Nozaki
发明人： Motoshige Kobayashi , Hideki Nozaki
IPC分类号： H01L2362
CPC分类号： H01L29/66333 , H01L29/36 , H01L29/7395
摘要： A semiconductor device comprises a first base layer for providing a PT-IGBT or IEGT structure, which includes a buffer layer and a collector layer provided in the buffer layer. A first activation rate, defined by an activated first conductivity type impurity density [cm−2] in the buffer layer due to SR analysis/a first conductivity type impurity density [cm−2] in the buffer layer due to SIMS analysis is given by 25% or more, and a second activation rate, defined by an activated second conductivity type impurity density [cm−2] in the collector layer due to SR analysis/a second conductivity type impurity density [cm−2] in the collector layer duet to SIMS analysis is given by more than 0% and 10% or less.
摘要翻译：半导体器件包括用于提供PT-IGBT或IEGT结构的第一基极层，其包括设置在缓冲层中的缓冲层和集电极层。由缓冲层中的SR分析/第一导电型杂质浓度[cm -2]在缓冲层中由于SIMS而由活化的第一导电类型杂质密度[cm -2]限定的第一活化速率分析为25％以上，由于SR分析/第二导电型杂质密度[cm -1]，在集电体层中由活化的第二导电型杂质浓度[cm -2]限定的第二活化率， 2>]在集电极二极管到SIMS分析中给出了超过0％和10％以下。

9. 发明授权

US07737531B2 Wafer including a reinforcing flange formed upright at a periphery and method for manufacturing the same 有权
标题翻译：包括在周边直立形成的加强凸缘的晶片及其制造方法
公开(公告)号：US07737531B2
公开(公告)日：2010-06-15
申请号：US12253610
申请日：2008-10-17
申请人： Yasuharu Sugawara , Motoshige Kobayashi
发明人： Yasuharu Sugawara , Motoshige Kobayashi
IPC分类号： H01L29/06 , H01L21/311
CPC分类号： H01L29/0657 , H01L21/02035 , H01L21/78 , H01L29/66348
摘要： A wafer with an orientation notch being cut in a portion of its circumference, the wafer includes: a reinforcing flange formed upright at periphery; and a thin section surrounded by the reinforcing flange and having a smaller thickness than the reinforcing flange. The reinforcing flange includes a circumferential portion formed upright along the circumference and a notch portion formed upright near the orientation notch, and a width of the circumferential portion as viewed parallel to a major surface of the wafer is smaller than a depth of the orientation notch as viewed parallel to the major surface.
摘要翻译：具有在其圆周的一部分上被切割的取向凹口的晶片，所述晶片包括：在周边竖立形成的加强凸缘; 以及由加强凸缘包围并且具有比加强凸缘更小的厚度的薄部分。加强凸缘包括沿着圆周竖直形成的圆周部分和在定位凹口附近形成的切口部分，并且与晶片的主表面平行的圆周部分的宽度小于定向切口的深度，平行于主表面观察。

10. 发明申请

US20090102020A1 WAFER AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：其制造方法及其制造方法
公开(公告)号：US20090102020A1
公开(公告)日：2009-04-23
申请号：US12253610
申请日：2008-10-17
申请人： Yasuharu SUGAWARA , Motoshige Kobayashi
发明人： Yasuharu SUGAWARA , Motoshige Kobayashi
IPC分类号： H01L29/06 , H01L21/311
CPC分类号： H01L29/0657 , H01L21/02035 , H01L21/78 , H01L29/66348
摘要： A wafer with an orientation notch being cut in a portion of its circumference, the wafer includes: a reinforcing flange formed upright at periphery; and a thin section surrounded by the reinforcing flange and having a smaller thickness than the reinforcing flange. The reinforcing flange includes a circumferential portion formed upright along the circumference and a notch portion formed upright near the orientation notch, and a width of the circumferential portion as viewed parallel to a major surface of the wafer is smaller than a depth of the orientation notch as viewed parallel to the major surface.
摘要翻译：具有在其圆周的一部分上被切割的取向凹口的晶片，所述晶片包括：在周边竖立形成的加强凸缘; 以及由加强凸缘包围并且具有比加强凸缘更小的厚度的薄部分。加强凸缘包括沿着圆周竖直形成的圆周部分和在定位凹口附近形成的切口部分，并且与晶片的主表面平行的圆周部分的宽度小于定向切口的深度，平行于主表面观察。

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