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1. 发明授权

US09177857B2 Semiconductor device with high reliability and manufacturing method thereof 有权
标题翻译：具有高可靠性的半导体器件及其制造方法
公开(公告)号：US09177857B2
公开(公告)日：2015-11-03
申请号：US12350448
申请日：2009-01-08
申请人： Daisuke Oshida , Toshiyuki Takewaki , Shinji Yokogawa
发明人： Daisuke Oshida , Toshiyuki Takewaki , Shinji Yokogawa
IPC分类号： H01L23/52 , H01L23/532 , H01L21/768 , H01L21/70
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76865 , H01L21/76873 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.
摘要翻译：提供了一种半导体器件，其包括衬底，在衬底上形成的绝缘膜，以及包含铜作为主要成分的不同宽度的多个金属配线和不同于铜的杂质。多个金属布线包括具有浓度分布的第一金属布线，其中杂质金属的浓度从堆叠方向的中心部分增加到表面，第二金属布线具有浓度分布，其中杂质金属的浓度从底面向堆叠方向的表面。此外，第二金属布线的宽度可以大于第一金属布线的宽度。

2. 发明申请

US20090184421A1 SEMICONDUCTOR DEVICE WITH HIGH RELIABILITY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有高可靠性和制造方法的半导体器件
公开(公告)号：US20090184421A1
公开(公告)日：2009-07-23
申请号：US12350448
申请日：2009-01-08
申请人： Daisuke Oshida , Toshiyuki Takewaki , Shinji Yokogawa
发明人： Daisuke Oshida , Toshiyuki Takewaki , Shinji Yokogawa
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76865 , H01L21/76873 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring.
摘要翻译：提供了一种半导体器件，其包括衬底，在衬底上形成的绝缘膜，以及包含铜作为主要成分的不同宽度的多个金属配线和不同于铜的杂质。多个金属布线包括具有浓度分布的第一金属布线，其中杂质金属的浓度从堆叠方向的中心部分增加到表面，第二金属布线具有浓度分布，其中杂质金属的浓度从底面向堆叠方向的表面。此外，第二金属布线的宽度可以大于第一金属布线的宽度。

3. 发明申请

US20050122460A1 Liquid crystal display device 有权
标题翻译：液晶显示装置
公开(公告)号：US20050122460A1
公开(公告)日：2005-06-09
申请号：US10997987
申请日：2004-11-29
申请人： Shinji Yokogawa , Yusuke Nogami
发明人： Shinji Yokogawa , Yusuke Nogami
IPC分类号： G02F1/1368 , G02F1/133 , G02F1/1343 , G02F1/136 , G02F1/1362
CPC分类号： G02F1/136259 , G02F1/134363 , G02F2001/136263
摘要： A slit portion is provided at the center of a shield common electrode which is overlapped with a drain wire as a different layer. When an interlayer short-circuiting occurs between the drain wire and the shield common electrode, it induces a critical defect on a screen display, however, a line defect can be repaired/extinguished by cutting both the sides of the slit at the short-circuited portion with laser repair and separating the short-circuited portion.
摘要翻译：在与漏极线重叠的屏蔽公共电极的中心处设置狭缝部分作为不同的层。当在漏极线和屏蔽公共电极之间发生层间短路时，它在屏幕显示器上引起严重的缺陷，然而，可以通过在短路的两侧切割狭缝来修复/熄灭线路缺陷部分具有激光修复和分离短路部分。

4. 发明授权

US08161428B2 Method of predicting reliability of semiconductor device, reliability prediction system using the same and storage medium storing program causing computer to execute the same 有权
标题翻译：预测半导体装置的可靠性的方法，使用该半导体装置的可靠性预测系统以及存储导致计算机执行该程序的存储介质的存储介质
公开(公告)号：US08161428B2
公开(公告)日：2012-04-17
申请号：US12385777
申请日：2009-04-20
申请人： Shinji Yokogawa
发明人： Shinji Yokogawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： An initial reliability of a semiconductor device is predicted before the design layout of a semiconductor product. A method of predicting the reliability of a semiconductor device according to the present invention: calculates the defect density of a plurality of wiring patterns on a wafer; extracts the critical area of a series of library elements formed of wiring patterns based on the defect density to determine the critical area value of each library element; determines a failure probability by wiring pattern from the result of a reliability test of the wiring pattern to form a correlation model from an expected value in which a defect is generated and which is obtained from the defect density and the failure probability of each wiring pattern; calculates the failure probability of each library element from the critical area value and the function of the correlation model; designs a layout of a semiconductor product with two library elements or more out of a series of the library elements combined together and calculates the reliability of the designed semiconductor device in consideration of the failure probability of the library elements combined together.
摘要翻译：在半导体产品的设计布局之前预测半导体器件的初始可靠性。根据本发明的预测半导体器件的可靠性的方法：计算晶片上的多个布线图案的缺陷密度; 基于缺陷密度提取由布线图形形成的一系列库元素的关键区域，以确定每个库元素的临界面积值; 根据布线图案的可靠性试验结果，根据布线图案的结果确定故障概率，从根据缺陷密度和各布线图案的故障概率得到缺陷的预期值形成相关模型; 从关键面积值和相关模型的函数计算每个库元素的失败概率; 设计具有组合在一起的一系列库元件中的两个库元件或更多的半导体产品的布局，并且考虑到库元件组合在一起的故障概率来计算设计的半导体器件的可靠性。

5. 发明授权

US07352432B2 Liquid crystal display device 有权
标题翻译：液晶显示装置
公开(公告)号：US07352432B2
公开(公告)日：2008-04-01
申请号：US10997987
申请日：2004-11-29
申请人： Shinji Yokogawa , Yusuki Nogami
发明人： Shinji Yokogawa , Yusuki Nogami
IPC分类号： G02F1/13
CPC分类号： G02F1/136259 , G02F1/134363 , G02F2001/136263
摘要： A slit portion is provided at the center of a shield common electrode which is overlapped with a drain wire as a different layer. When an interlayer short-circuiting occurs between the drain wire and the shield common electrode, it induces a critical defect on a screen display, however, a line defect can be repaired/extinguished by cutting both the sides of the slit at the short-circuited portion with laser repair and separating the short-circuited portion.
摘要翻译：在与漏极线重叠的屏蔽公共电极的中心处设置狭缝部分作为不同的层。当在漏极线和屏蔽公共电极之间发生层间短路时，它在屏幕显示器上引起严重的缺陷，然而，可以通过在短路的两侧切割狭缝来修复/熄灭线路缺陷部分具有激光修复和分离短路部分。

6. 发明申请

US20100095258A1 Wiring layout method of integrated circuit and computer-readable medium storing a program executed by a computer to execute the same 失效
标题翻译：集成电路的布线方法和存储由计算机执行的程序的计算机可读介质
公开(公告)号：US20100095258A1
公开(公告)日：2010-04-15
申请号：US12588995
申请日：2009-11-04
申请人： Shinji Yokogawa , Hideaki Tsuchiya
发明人： Shinji Yokogawa , Hideaki Tsuchiya
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A wiring layout method includes designing a layout of a power wiring for an integrated circuit; designing a layout of plural signal wirings for the integrated circuit; comparing the signal frequency; classifying the signal wirings; calculating an evaluation value of a temperature rise; and modifying the layouts of the integrated circuit.In the comparing the signal frequency, the signal frequency of each of the signal wirings is compared with a predetermined reference frequency. In the classifying the signal wirings, the signal wirings are classified into a first group in which a signal frequency is equal to or higher than a reference frequency and a second group in which a signal frequency is lower than the reference frequency. In the calculating an evaluation value of a temperature rise, an evaluation value of a temperature rise is calculated by excluding the temperature rise caused by a power consumption of the signal wirings of the first group. And in the modifying the layouts, the layouts of the integrated circuit is modified if the evaluation value is over the predetermined allowable value.
摘要翻译：布线布置方法包括设计用于集成电路的电力布线的布局; 设计用于集成电路的多个信号布线的布局; 比较信号频率; 分类信号线; 计算温升的评价值; 并修改集成电路的布局。在比较信号频率时，将每个信号布线的信号频率与预定的参考频率进行比较。在对信号配线进行分类时，信号配线分为信号频率等于或高于参考频率的第一组，信号频率低于参考频率的第二组。在计算温度上升的评估值时，通过排除由第一组的信号配线的功耗引起的温度上升来计算温升的评价值。并且在修改布局时，如果评估值超过预定的允许值，则修改集成电路的布局。

7. 发明授权

US06787802B2 Semiconductor device including evaluation elements 失效
标题翻译：包括评估元件的半导体装置
公开(公告)号：US06787802B2
公开(公告)日：2004-09-07
申请号：US10454469
申请日：2003-06-05
申请人： Shinji Yokogawa
发明人： Shinji Yokogawa
IPC分类号： H01L2358
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device including evaluation elements comprising a plurality of first wirings composed of a first wiring layer, a plurality of second wirings composed of a second wiring layer and vias connecting the first wirings and the second wirings, the first wirings and the second wirings are formed in directions almost perpendicular with each other, and relative to the plurality of first wirings juxtaposed with a prescribed interval, the plurality of second wirings connecting the adjacent first wirings are juxtaposed in the length direction of the first wirings, and a plurality of current paths are formed in parallel.
摘要翻译：在包括由第一布线层，由第二布线层构成的多个第二布线和连接第一布线和第二布线的通路构成的多个第一布线的评估元件的半导体器件中，第一布线和第二布线是形成在彼此大致垂直的方向上，并且相对于以规定间隔并列的多个第一布线，连接相邻的第一配线的多个第二配线在第一布线的长度方向上并列，并且多个电流路径并列形成。

8. 发明授权

US08209651B2 Wiring layout decision method of integrated circuit 失效
标题翻译：集成电路接线布局决策方法
公开(公告)号：US08209651B2
公开(公告)日：2012-06-26
申请号：US12588995
申请日：2009-11-04
申请人： Shinji Yokogawa , Hideaki Tsuchiya
发明人： Shinji Yokogawa , Hideaki Tsuchiya
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A wiring layout method includes designing a layout of a power wiring for an integrated circuit; designing a layout of plural signal wirings for the integrated circuit; comparing the signal frequency; classifying the signal wirings; calculating an evaluation value of a temperature rise; and modifying the layouts of the integrated circuit.
摘要翻译：布线布置方法包括设计用于集成电路的电力布线的布局; 设计用于集成电路的多个信号布线的布局; 比较信号频率; 分类信号线; 计算温升的评价值; 并修改集成电路的布局。

9. 发明授权

US07966587B2 Information storage medium on which is stored an interconnection program, interconnection method, interconnection apparatus, and semiconductor device 有权
标题翻译：其上存储有互连程序，互连方法，互连设备和半导体器件的信息存储介质
公开(公告)号：US07966587B2
公开(公告)日：2011-06-21
申请号：US11798981
申请日：2007-05-18
申请人： Hideaki Tsuchiya , Shinji Yokogawa
发明人： Hideaki Tsuchiya , Shinji Yokogawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081 , G06F2217/78
摘要： Conventionally, an excessively strict current limitation is often adopted. An interconnection apparatus includes an acquisition unit and a decision unit. The acquisition unit serves to acquire a current density and data rate of a region that a specific interconnect passes through. The decision unit serves to decide whether the temperature increase corresponding to the current density and the data rate acquired by the acquisition unit is within a permissible range.
摘要翻译：通常，通常采用过分严格的限制。互连装置包括采集单元和判定单元。采集单元用于获取特定互连通过的区域的电流密度和数据速率。决定单元用于判定与采集单元获取的电流密度和数据速率对应的温度升高是否在容许范围内。

10. 发明申请

US20090265155A1 Method of predicting reliability of semiconductor device, reliability prediction system using the same and storage medium storing program causing computer to execute the same 有权
标题翻译：预测半导体装置的可靠性的方法，使用该半导体装置的可靠性预测系统以及存储导致计算机执行该程序的存储介质的存储介质
公开(公告)号：US20090265155A1
公开(公告)日：2009-10-22
申请号：US12385777
申请日：2009-04-20
申请人： Shinji Yokogawa
发明人： Shinji Yokogawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： An initial reliability of a semiconductor device is predicted before the design layout of a semiconductor product. A method of predicting the reliability of a semiconductor device according to the present invention: calculates the defect density of a plurality of wiring patterns on a wafer; extracts the critical area of a series of library elements formed of wiring patterns based on the defect density to determine the critical area value of each library element; determines a failure probability by wiring pattern from the result of a reliability test of the wiring pattern to form a correlation model from an expected value in which a defect is generated and which is obtained from the defect density and the failure probability of each wiring pattern; calculates the failure probability of each library element from the critical area value and the function of the correlation model; designs a layout of a semiconductor product with two library elements or more out of a series of the library elements combined together and calculates the reliability of the designed semiconductor device in consideration of the failure probability of the library elements combined together.
摘要翻译：在半导体产品的设计布局之前预测半导体器件的初始可靠性。根据本发明的预测半导体器件的可靠性的方法：计算晶片上的多个布线图案的缺陷密度; 基于缺陷密度提取由布线图形形成的一系列库元素的关键区域，以确定每个库元素的临界面积值; 根据布线图案的可靠性试验结果，根据布线图案的结果确定故障概率，从根据缺陷密度和各布线图案的故障概率得到缺陷的预期值形成相关模型; 从关键面积值和相关模型的函数计算每个库元素的失败概率; 设计具有组合在一起的一系列库元件中的两个库元件或更多的半导体产品的布局，并且考虑到库元件组合在一起的故障概率来计算设计的半导体器件的可靠性。

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