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1. 发明授权

US07535099B2 Sintered metallic thermal interface materials for microelectronic cooling assemblies 有权
标题翻译：用于微电子冷却组件的烧结金属热界面材料
公开(公告)号：US07535099B2
公开(公告)日：2009-05-19
申请号：US11528123
申请日：2006-09-26
申请人： Daewoong Suh , Chi-won Hwang
发明人： Daewoong Suh , Chi-won Hwang
IPC分类号： H01L23/373
CPC分类号： H01L23/3736 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15312 , H01L2924/16195 , H01L2924/00 , H01L2224/0401
摘要： A microelectronic cooling assembly and method for fabricating the same are described. In one example, a microelectronic cooling assembly includes a microelectronic device, a heat spreader, and a thermal interface material (TIM) that thermally joins the microelectronic device and heat spreader, the TIM comprising a sintered metallic nanopaste.
摘要翻译：描述了一种微电子冷却组件及其制造方法。在一个示例中，微电子冷却组件包括微电子器件，散热器和热接合微电子器件和散热器的热界面材料（TIM），TIM包含烧结金属纳米糊剂。

2. 发明申请

US20070227627A1 Solder composition having dispersoid particles for increased creep resistance 审中-公开
标题翻译：具有分散质颗粒的焊料组合物用于增加耐蠕变性
公开(公告)号：US20070227627A1
公开(公告)日：2007-10-04
申请号：US11395667
申请日：2006-03-30
申请人： Daewoong Suh , Chi-won Hwang
发明人： Daewoong Suh , Chi-won Hwang
IPC分类号： C22C12/00 , C22C28/00
CPC分类号： C22C12/00 , B23K35/00 , B23K35/0244 , B23K35/26 , B23K35/262 , B23K35/264 , B23K35/327 , B23K2101/40 , C22C1/03 , C22C1/05 , C22C28/00 , C22C30/00 , C22C32/00
摘要： A solder composition is provided. A solder composition has a solder matrix material and dispersoid particles in the solder matrix material. The solder matrix material has a relatively low melting temperature and the dispersoid particles have a relatively high melting temperature.
摘要翻译：提供焊料组合物。焊料组合物在焊料基质材料中具有焊料基质材料和分散质颗粒。焊料基质材料具有相对低的熔融温度，并且分散质颗粒具有相对较高的熔融温度。

3. 发明申请

US20080073776A1 Sintered metallic thermal interface materials for microelectronic cooling assemblies 有权
标题翻译：用于微电子冷却组件的烧结金属热界面材料
公开(公告)号：US20080073776A1
公开(公告)日：2008-03-27
申请号：US11528123
申请日：2006-09-26
申请人： Daewoong Suh , Chi-won Hwang
发明人： Daewoong Suh , Chi-won Hwang
IPC分类号： H01L23/34 , H01L21/00
CPC分类号： H01L23/3736 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15312 , H01L2924/16195 , H01L2924/00 , H01L2224/0401
摘要： A microelectronic cooling assembly and method for fabricating the same are described. In one example, a microelectronic cooling assembly includes a microelectronic device, a heat spreader, and a thermal interface material (TIM) that thermally joins the microelectronic device and heat spreader, the TIM comprising a sintered metallic nanopaste.
摘要翻译：描述了一种微电子冷却组件及其制造方法。在一个示例中，微电子冷却组件包括微电子器件，散热器和热接合微电子器件和散热器的热界面材料（TIM），TIM包含烧结金属纳米糊剂。

4. 发明申请

US20080295325A1 MULTI-CHIP PACKAGING USING AN INTERPOSER SUCH AS A SILICON BASED INTERPOSER WITH THROUGH-SILICON-VIAS 有权
标题翻译：多芯片封装使用插座等作为基于硅的间插器与穿透硅
公开(公告)号：US20080295325A1
公开(公告)日：2008-12-04
申请号：US11755735
申请日：2007-05-30
申请人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
发明人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
IPC分类号： H05K3/36
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/147 , H01L25/0655 , H01L2224/81203 , H01L2224/81815 , H01L2924/10253 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49163 , Y10T29/49165 , H01L2924/00
摘要： The formation of electronic assemblies, including assemblies having an interposer, are described. In one embodiment, a method includes forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface of the body, the electrically conductive layer defining a first metal pad layer on the upper surface and a second metal pad layer in contact with the first metal pad layer, the second metal pad layer having a denser pitch between adjacent pads than the first metal pad layer. The method also includes forming a dielectric layer between the adjacent metal pads in the first and second pad layers. The method also includes coupling a plurality of elements to the second metal pad layer. After the coupling the elements, the method includes thinning the body through a lower surface and exposing the electrically insulating layer in the vias. The method also includes removing a portion of the electrically insulating layer in the vias, and coupling the electrically conductive layer to a substrate, wherein the body is positioned between the elements and the substrate. Other embodiments are described and claimed.
摘要翻译：描述了包括具有插入件的组件的电子组件的形成。在一个实施例中，一种方法包括形成多个部分延伸通过主体的通孔，通孔包括由主体限定的侧壁。绝缘层形成在主体的侧壁和上表面上。导电层形成在通孔的绝缘层上和主体的上表面上，导电层在上表面上限定第一金属焊盘层和与第一金属焊盘层接触的第二金属焊盘层，所述第二金属焊盘层在相邻焊盘之间具有比所述第一金属焊盘层更密的间距。该方法还包括在第一和第二焊盘层中的相邻金属焊盘之间形成电介质层。该方法还包括将多个元件耦合到第二金属焊盘层。在耦合这些元件之后，该方法包括通过下表面使本体变薄并暴露通孔中的电绝缘层。该方法还包括去除通孔中电绝缘层的一部分，以及将导电层耦合到衬底，其中本体位于元件和衬底之间。描述和要求保护其他实施例。

5. 发明授权

US08391016B2 Carbon nanotube-reinforced solder caps, and chip packages and systems containing same 有权
标题翻译：碳纳米管增强焊锡帽，以及包含其的芯片封装和系统
公开(公告)号：US08391016B2
公开(公告)日：2013-03-05
申请号：US12583831
申请日：2009-08-25
申请人： Chi-won Hwang
发明人： Chi-won Hwang
IPC分类号： H01L23/488
CPC分类号： H01L23/49816 , H01L23/49877 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/742 , H01L24/81 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/11003 , H01L2224/11332 , H01L2224/11822 , H01L2224/13099 , H01L2224/13609 , H01L2224/16 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/19042 , H01L2924/351 , Y10T428/12007 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A carbon nanotube solder is formed on a substrate of an integrated circuit package. The carbon nanotube solder exhibits high heat and electrical conductivities. The carbon nanotube solder is used as a solder microcap on a metal bump for communication between an integrated circuit device and external structures.
摘要翻译：在集成电路封装的基板上形成碳纳米管焊料。碳纳米管焊料表现出高的热和电导率。碳纳米管焊料用作金属凸块上的焊料微帽，用于集成电路器件和外部结构之间的连接。

6. 发明授权

US07952203B2 Methods of forming C4 round dimple metal stud bumps for fine pitch packaging applications and structures formed thereby 有权
标题翻译：形成用于细间距包装应用的C4圆形凹坑金属柱凸块的方法和由此形成的结构
公开(公告)号：US07952203B2
公开(公告)日：2011-05-31
申请号：US12231167
申请日：2008-08-29
申请人： Chi-won Hwang
发明人： Chi-won Hwang
IPC分类号： H01L23/485
CPC分类号： H01L24/11 , H01L21/76807 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05559 , H01L2224/1134 , H01L2224/13005 , H01L2224/13006 , H01L2224/13023 , H01L2924/00013 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/207 , H01L2224/13099 , H01L2224/29099 , H01L2924/00
摘要： Methods of forming microelectronic device structures are described. Those methods may include forming a passivation layer on a substrate, wherein the substrate comprises an array of conductive structures, forming a first via in the passivation layer, forming a second via in the passivation layer that exposes at least one of the conductive structures in the array, and wherein the second via is formed within the first via space to form a step via, and forming a conductive material in the step via, wherein a round dimple is formed in the conductive material.
摘要翻译：描述形成微电子器件结构的方法。这些方法可以包括在衬底上形成钝化层，其中衬底包括导电结构阵列，在钝化层中形成第一通孔，在钝化层中形成第二通道，该第二通孔暴露出至少一个导电结构并且其中所述第二通孔形成在所述第一通孔空间内以形成台阶通孔，并且在所述台阶通孔中形成导电材料，其中在所述导电材料中形成圆形凹坑。

7. 发明授权

US08387240B2 Methods for making multi-chip packaging using an interposer 有权
标题翻译：使用插入片进行多芯片封装的方法
公开(公告)号：US08387240B2
公开(公告)日：2013-03-05
申请号：US12955816
申请日：2010-11-29
申请人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
发明人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
IPC分类号： H01K3/10
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/147 , H01L25/0655 , H01L2224/81203 , H01L2224/81815 , H01L2924/10253 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49163 , Y10T29/49165 , H01L2924/00
摘要： In one embodiment, a method includes forming a plurality of vias partially through a body, the vias including sidewalls defined by the body. An electrically insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. The body is thinned through a lower surface and the electrically insulating layer in the vias is exposed. After the thinning, a portion of the electrically insulating layer in the, vias is removed. The body is coupled to a substrate.
摘要翻译：在一个实施例中，一种方法包括通过主体部分地形成多个通孔，通孔包括由身体限定的侧壁。电绝缘层形成在主体的侧壁和上表面上。在通孔和上表面上的绝缘层上形成导电层，导电层限定上表面上的第一金属焊盘和与第一金属焊盘接触的第二金属焊盘，第二金属焊盘具有较密的间距比第一金属垫。在相邻的第一金属焊盘之间和相邻的第二金属焊盘之间形成介电层。身体通过下表面变薄，并且通孔中的电绝缘层被暴露。在变薄之后，去除通孔中的电绝缘层的一部分。主体耦合到基板。

8. 发明申请

US20170004978A1 METHODS OF FORMING HIGH DENSITY METAL WIRING FOR FINE LINE AND SPACE PACKAGING APPLICATIONS AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：形成高密度金属接线的方法和空间包装应用及其形成的结构
公开(公告)号：US20170004978A1
公开(公告)日：2017-01-05
申请号：US11968116
申请日：2007-12-31
申请人： Chi-won Hwang , Yoshihiro Tomita
发明人： Chi-won Hwang , Yoshihiro Tomita
IPC分类号： H01L21/48 , H05K3/12 , H05K3/40 , H01L23/498 , H05K3/00
CPC分类号： H01L21/486 , C09D11/52 , H01L21/4867 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L2924/0002 , H05K3/0023 , H05K3/0026 , H05K3/107 , H05K3/1216 , H05K3/1258 , H05K3/1291 , H05K3/4053 , H05K3/465 , H05K3/4664 , H05K2201/0257 , H05K2203/1131 , H01L2924/00
摘要： Methods of forming microelectronic device structures are described. Those methods may include forming at least one opening through a build up structure and a photo sensitive material disposed on the build up structure, wherein the build up structure comprises a portion of a package substrate, filling the at least one opening with a metal containing nanopaste, and sintering the metal containing nanopaste to form a bulk property metal structure in the at least one opening.
摘要翻译：描述形成微电子器件结构的方法。这些方法可以包括通过建立结构和设置在堆积结构上的感光材料形成至少一个开口，其中堆积结构包括封装衬底的一部分，用含金属纳米糊剂填充至少一个开口并且在所述至少一个开口中烧结含有金属的纳米糊剂以形成本体特性的金属结构。

9. 发明授权

US07882628B2 Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias 有权
标题翻译：使用诸如具有通硅通孔的硅基插入件的插入器的多芯片封装
公开(公告)号：US07882628B2
公开(公告)日：2011-02-08
申请号：US11755733
申请日：2007-05-30
申请人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
发明人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
IPC分类号： H01K3/10
CPC分类号： H01L23/147 , H01L23/481 , H01L23/49827 , H01L25/0655 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05548 , H01L2224/05569 , H01L2224/05639 , H01L2224/05647 , H01L2224/05684 , H01L2224/16225 , H01L2924/10253 , H01L2924/15311 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49165 , Y10T29/49169 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/04941
摘要： The formation of electronic assemblies is described. One embodiment includes providing a body and forming a first metal pad layer on a first surface thereof. A second metal pad layer is formed in contact with the first metal pad layer, the second metal pad layer having a denser pitch than the first metal pad layer. A dielectric layer is formed between the metal pads in the first and second metal pad layers. Vias extending through the body from a second surface thereof are formed, the vias exposing the first metal pad layer. An insulating layer is formed on via sidewalls and on the second surface, and an electrically conductive layer formed on the insulating layer and on the exposed surface of the first metal layer. Elements are coupled to the second metal pad layer and the electrically conductive layer coupled to a substrate. Other embodiments are described and claimed.
摘要翻译：描述了电子组件的形成。一个实施例包括提供主体并在其第一表面上形成第一金属垫层。形成与第一金属焊盘层接触的第二金属焊盘层，第二金属焊盘层的间距比第一金属焊盘层更致密。在第一和第二金属焊盘层中的金属焊盘之间形成电介质层。形成从其第二表面延伸穿过本体的通孔，露出第一金属垫层的通孔。在通孔侧壁和第二表面上形成绝缘层，以及形成在第一金属层的绝缘层和暴露表面上的导电层。元件耦合到第二金属焊盘层和耦合到衬底的导电层。描述和要求保护其他实施例。

10. 发明申请

US20080295329A1 MULTI-CHIP PACKAGING USING AN INTERPOSER SUCH AS A SILICON BASED INTERPOSER WITH THROUGH-SILICON-VIAS 有权
标题翻译：多芯片封装使用插座等作为基于硅的间插器与穿透硅
公开(公告)号：US20080295329A1
公开(公告)日：2008-12-04
申请号：US11755733
申请日：2007-05-30
申请人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
发明人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
IPC分类号： H05K1/02 , H05K1/03 , H05K3/10 , H05K3/34
CPC分类号： H01L23/147 , H01L23/481 , H01L23/49827 , H01L25/0655 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05186 , H01L2224/05548 , H01L2224/05569 , H01L2224/05639 , H01L2224/05647 , H01L2224/05684 , H01L2224/16225 , H01L2924/10253 , H01L2924/15311 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49165 , Y10T29/49169 , H01L2924/00 , H01L2924/00014 , H01L2924/013 , H01L2924/04941
摘要： The formation of electronic assemblies, including assemblies having an interposer, are described. In one embodiment, a method includes providing a body and forming a first metal pad layer on a first surface thereof. A second metal pad layer is formed in contact with the first patterned metal pad layer, the second metal pad layer having a denser pitch between adjacent pads than the first metal pad layer. A dielectric layer is formed between the adjacent metal pads in the first and second metal pad layers. After the forming the first and second metal pad layers and the dielectric layer, the method includes forming a plurality of vias extending through the body from a second surface thereof, the vias extending through a thickness of the body and exposing the first metal pad layer. The method also includes forming an insulating layer on sidewalls of the vias and on the second surface, and forming an electrically conductive layer on the insulating layer and on the exposed surface of the first metal layer. The method also includes coupling a plurality of elements to the second metal pad layer and coupling the electrically conductive layer to a substrate, the body being positioned between the elements and the substrate. Other embodiments are described and claimed.
摘要翻译：描述了包括具有插入件的组件的电子组件的形成。在一个实施例中，一种方法包括提供主体并在其第一表面上形成第一金属垫层。第二金属焊盘层形成为与第一图案化金属焊盘层接触，第二金属焊盘层在相邻焊盘之间具有比第一金属焊盘层更紧密的间距。在第一和第二金属焊盘层中的相邻金属焊盘之间形成电介质层。在形成第一和第二金属垫层和电介质层之后，该方法包括形成从其第二表面延伸通过本体的多个通孔，通孔延伸穿过本体的厚度并暴露第一金属垫层。该方法还包括在通孔的侧壁和第二表面上形成绝缘层，并且在绝缘层和第一金属层的暴露表面上形成导电层。该方法还包括将多个元件耦合到第二金属焊盘层并将导电层耦合到基板，该主体位于元件和基板之间。描述和要求保护其他实施例。

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