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1. 发明申请

US20110067236A1 MULTI-CHIP PACKAGING USING AN INTERPOSER SUCH AS A SILICON BASED INTERPOSER WITH THROUGH-SILICON-VIAS 有权
标题翻译：多芯片封装使用插座等作为基于硅的间插器与穿透硅
公开(公告)号：US20110067236A1
公开(公告)日：2011-03-24
申请号：US12955816
申请日：2010-11-29
申请人： Sriram MUTHUKUMAR , Raul MANCERA , Yoshihiro TOMITA , Chi-won HWANG
发明人： Sriram MUTHUKUMAR , Raul MANCERA , Yoshihiro TOMITA , Chi-won HWANG
IPC分类号： H01K3/10
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/147 , H01L25/0655 , H01L2224/81203 , H01L2224/81815 , H01L2924/10253 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49163 , Y10T29/49165 , H01L2924/00
摘要： The formation of electronic assemblies, including assemblies having an interposer, are described. In one embodiment, a method includes forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface of the body, the electrically conductive layer defining a first metal pad layer on the upper surface and a second metal pad layer in contact with the first metal pad layer, the second metal pad layer having a denser pitch between adjacent pads than the first metal pad layer. The method also includes forming a dielectric layer between the adjacent metal pads in the first and second pad layers. The method also includes coupling a plurality of elements to the second metal pad layer. After the coupling the elements, the method includes thinning the body through a lower surface and exposing the electrically insulating layer in the vias. The method also includes removing a portion of the electrically insulating layer in the vias, and coupling the electrically conductive layer to a substrate, wherein the body is positioned between the elements and the substrate. Other embodiments are described and claimed.
摘要翻译：描述了包括具有插入件的组件的电子组件的形成。在一个实施例中，一种方法包括形成多个部分延伸通过主体的通孔，通孔包括由主体限定的侧壁。绝缘层形成在主体的侧壁和上表面上。导电层形成在通孔的绝缘层上和主体的上表面上，导电层在上表面上限定第一金属焊盘层和与第一金属焊盘层接触的第二金属焊盘层，所述第二金属焊盘层在相邻焊盘之间具有比所述第一金属焊盘层更密的间距。该方法还包括在第一和第二焊盘层中的相邻金属焊盘之间形成电介质层。该方法还包括将多个元件耦合到第二金属焊盘层。在耦合这些元件之后，该方法包括通过下表面使本体变薄并暴露通孔中的电绝缘层。该方法还包括去除通孔中电绝缘层的一部分，以及将导电层耦合到衬底，其中主体位于元件和衬底之间。描述和要求保护其他实施例。

2. 发明申请

US20080295325A1 MULTI-CHIP PACKAGING USING AN INTERPOSER SUCH AS A SILICON BASED INTERPOSER WITH THROUGH-SILICON-VIAS 有权
标题翻译：多芯片封装使用插座等作为基于硅的间插器与穿透硅
公开(公告)号：US20080295325A1
公开(公告)日：2008-12-04
申请号：US11755735
申请日：2007-05-30
申请人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
发明人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
IPC分类号： H05K3/36
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/147 , H01L25/0655 , H01L2224/81203 , H01L2224/81815 , H01L2924/10253 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49163 , Y10T29/49165 , H01L2924/00
摘要： The formation of electronic assemblies, including assemblies having an interposer, are described. In one embodiment, a method includes forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface of the body, the electrically conductive layer defining a first metal pad layer on the upper surface and a second metal pad layer in contact with the first metal pad layer, the second metal pad layer having a denser pitch between adjacent pads than the first metal pad layer. The method also includes forming a dielectric layer between the adjacent metal pads in the first and second pad layers. The method also includes coupling a plurality of elements to the second metal pad layer. After the coupling the elements, the method includes thinning the body through a lower surface and exposing the electrically insulating layer in the vias. The method also includes removing a portion of the electrically insulating layer in the vias, and coupling the electrically conductive layer to a substrate, wherein the body is positioned between the elements and the substrate. Other embodiments are described and claimed.
摘要翻译：描述了包括具有插入件的组件的电子组件的形成。在一个实施例中，一种方法包括形成多个部分延伸通过主体的通孔，通孔包括由主体限定的侧壁。绝缘层形成在主体的侧壁和上表面上。导电层形成在通孔的绝缘层上和主体的上表面上，导电层在上表面上限定第一金属焊盘层和与第一金属焊盘层接触的第二金属焊盘层，所述第二金属焊盘层在相邻焊盘之间具有比所述第一金属焊盘层更密的间距。该方法还包括在第一和第二焊盘层中的相邻金属焊盘之间形成电介质层。该方法还包括将多个元件耦合到第二金属焊盘层。在耦合这些元件之后，该方法包括通过下表面使本体变薄并暴露通孔中的电绝缘层。该方法还包括去除通孔中电绝缘层的一部分，以及将导电层耦合到衬底，其中本体位于元件和衬底之间。描述和要求保护其他实施例。

3. 发明申请

US20070152194A1 Nano-scale particle paste for wiring microelectronic devices using deposition and ink-jet printing 有权
标题翻译：用于使用沉积和喷墨印刷布线微电子器件的纳米级粒子糊
公开(公告)号：US20070152194A1
公开(公告)日：2007-07-05
申请号：US11322504
申请日：2005-12-30
申请人： Devendra Natekar , Yoshihiro Tomita , Chi-Won Hwang
发明人： Devendra Natekar , Yoshihiro Tomita , Chi-Won Hwang
IPC分类号： C23C16/00 , B05D5/00
CPC分类号： H05K1/097 , B82Y10/00 , H01L24/27 , H01L24/29 , H01L24/83 , H01L25/0657 , H01L2224/29 , H01L2224/29101 , H01L2224/29298 , H01L2224/838 , H01L2225/06541 , H01L2225/06575 , H01L2924/00011 , H01L2924/00013 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H05K3/125 , H05K2201/026 , H05K2203/013 , H01L2924/00 , H01L2924/3512 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929
摘要： Nano-scale particle paste may be used for on-die routing and other applications using deposition and ink-jet printing. A metal paste is applied to a surface of a die to electrically couple two spaced apart connection points of the die. Alternatively, or in addition, the paste may contain carbon nanotubes. The paste may be used on other surfaces as well.
摘要翻译：纳米级粒子糊可以用于使用沉积和喷墨打印的管芯路由和其它应用。将金属膏施加到模具的表面以电耦合模具的两个间隔开的连接点。或者或另外，糊状物可以含有碳纳米管。糊也可用于其他表面。

4. 发明授权

US08391016B2 Carbon nanotube-reinforced solder caps, and chip packages and systems containing same 有权
标题翻译：碳纳米管增强焊锡帽，以及包含其的芯片封装和系统
公开(公告)号：US08391016B2
公开(公告)日：2013-03-05
申请号：US12583831
申请日：2009-08-25
申请人： Chi-won Hwang
发明人： Chi-won Hwang
IPC分类号： H01L23/488
CPC分类号： H01L23/49816 , H01L23/49877 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/742 , H01L24/81 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/11003 , H01L2224/11332 , H01L2224/11822 , H01L2224/13099 , H01L2224/13609 , H01L2224/16 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/19042 , H01L2924/351 , Y10T428/12007 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A carbon nanotube solder is formed on a substrate of an integrated circuit package. The carbon nanotube solder exhibits high heat and electrical conductivities. The carbon nanotube solder is used as a solder microcap on a metal bump for communication between an integrated circuit device and external structures.
摘要翻译：在集成电路封装的基板上形成碳纳米管焊料。碳纳米管焊料表现出高的热和电导率。碳纳米管焊料用作金属凸块上的焊料微帽，用于集成电路器件和外部结构之间的连接。

5. 发明授权

US07952203B2 Methods of forming C4 round dimple metal stud bumps for fine pitch packaging applications and structures formed thereby 有权
标题翻译：形成用于细间距包装应用的C4圆形凹坑金属柱凸块的方法和由此形成的结构
公开(公告)号：US07952203B2
公开(公告)日：2011-05-31
申请号：US12231167
申请日：2008-08-29
申请人： Chi-won Hwang
发明人： Chi-won Hwang
IPC分类号： H01L23/485
CPC分类号： H01L24/11 , H01L21/76807 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05559 , H01L2224/1134 , H01L2224/13005 , H01L2224/13006 , H01L2224/13023 , H01L2924/00013 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/207 , H01L2224/13099 , H01L2224/29099 , H01L2924/00
摘要： Methods of forming microelectronic device structures are described. Those methods may include forming a passivation layer on a substrate, wherein the substrate comprises an array of conductive structures, forming a first via in the passivation layer, forming a second via in the passivation layer that exposes at least one of the conductive structures in the array, and wherein the second via is formed within the first via space to form a step via, and forming a conductive material in the step via, wherein a round dimple is formed in the conductive material.
摘要翻译：描述形成微电子器件结构的方法。这些方法可以包括在衬底上形成钝化层，其中衬底包括导电结构阵列，在钝化层中形成第一通孔，在钝化层中形成第二通道，该第二通孔暴露出至少一个导电结构并且其中所述第二通孔形成在所述第一通孔空间内以形成台阶通孔，并且在所述台阶通孔中形成导电材料，其中在所述导电材料中形成圆形凹坑。

6. 发明申请

US20090057378A1 IN-SITU CHIP ATTACHMENT USING SELF-ORGANIZING SOLDER 审中-公开
标题翻译：使用自组织焊接机的现场芯片连接
公开(公告)号：US20090057378A1
公开(公告)日：2009-03-05
申请号：US11845174
申请日：2007-08-27
申请人： Chi-Won Hwang , Daewoong Suh
发明人： Chi-Won Hwang , Daewoong Suh
IPC分类号： B23K35/36 , B23K1/00
CPC分类号： B23K3/0623 , B23K35/0244 , B23K35/025 , B23K35/262 , B23K35/264 , B23K35/282 , B23K35/3006 , B23K35/3013 , B23K35/302 , B23K35/3033 , B23K35/3046 , B23K35/362 , B23K2101/40 , H05K3/323 , H05K3/3436 , H05K3/3484 , H05K2201/10977
摘要： An in-situ chip attachment process uses a self-organizing solder paste composed of a synthetic resin organic flux and solder particles having a mean diameter that falls between around 0.1 μm and around 10 μm. The process is carried out by blanket depositing the solder paste on a first substrate having a first metal structure, pressing a second substrate having a second metal structure into the solder paste such that the second metal structure is aligned with the first metal structure and a gap exists between the first and second metal structures, heating the solder paste to a reflow temperature for a time duration sufficient to cause the solder particles to coalesce and form an electrical connection between the first and second metal structures. The reflow temperature ranges from around 100° C. to around 500° C. The time duration ranges between around 30 seconds and around 900 seconds.
摘要翻译：原位芯片附接工艺使用由合成树脂有机焊剂和平均直径在约0.1μm至约10μm之间的焊料颗粒组成的自组织焊膏。该工艺是通过在具有第一金属结构的第一衬底上将焊膏铺放在一起而进行的，将具有第二金属结构的第二衬底压入焊膏中，使得第二金属结构与第一金属结构对准，存在于第一和第二金属结构之间，将焊膏加热至回流温度足以使焊料颗粒聚结并形成第一和第二金属结构之间的电连接的持续时间。回流温度范围为约100°C至约500°C。持续时间范围在约30秒至约900秒之间。

7. 发明授权

US07268077B2 Carbon nanotube reinforced metallic layer 有权
公开(公告)号：US07268077B2
公开(公告)日：2007-09-11
申请号：US11292690
申请日：2005-12-02
申请人： Chi-Won Hwang
发明人： Chi-Won Hwang
IPC分类号： H01L21/44
CPC分类号： H01L24/73 , B82Y10/00 , H01L23/3128 , H01L23/49811 , H01L23/49877 , H01L23/585 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/48 , H01L24/81 , H01L2224/11822 , H01L2224/13099 , H01L2224/1358 , H01L2224/16145 , H01L2224/16225 , H01L2224/16237 , H01L2224/48091 , H01L2224/73257 , H01L2224/81136 , H01L2224/81193 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/07811 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/351 , H05K3/244 , H05K3/328 , H05K2201/026 , H01L2224/29099 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method and apparatus including an interconnect structure having a surface, a plurality of nanotubes disposed adjacent to the surface, and a metallic layer disposed adjacent to the surface and substantially including the nanotubes. An assembly may include a first embodiment of an apparatus as described, and may further include a second such embodiment at least one of physically and electrically coupled to the first embodiment.

8. 发明申请

US20070128883A1 Carbon nanotube reinforced metallic layer 有权
标题翻译：碳纳米管增强金属层
公开(公告)号：US20070128883A1
公开(公告)日：2007-06-07
申请号：US11292690
申请日：2005-12-02
申请人： Chi-Won Hwang
发明人： Chi-Won Hwang
IPC分类号： H01L21/31
CPC分类号： H01L24/73 , B82Y10/00 , H01L23/3128 , H01L23/49811 , H01L23/49877 , H01L23/585 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/48 , H01L24/81 , H01L2224/11822 , H01L2224/13099 , H01L2224/1358 , H01L2224/16145 , H01L2224/16225 , H01L2224/16237 , H01L2224/48091 , H01L2224/73257 , H01L2224/81136 , H01L2224/81193 , H01L2224/81801 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/07811 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/351 , H05K3/244 , H05K3/328 , H05K2201/026 , H01L2224/29099 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method and apparatus including an interconnect structure having a surface, a plurality of nanotubes disposed adjacent to the surface, and a metallic layer disposed adjacent to the surface and substantially including the nanotubes. An assembly may include a first embodiment of an apparatus as described, and may further include a second such embodiment at least one of physically and electrically coupled to the first embodiment.
摘要翻译：一种包括具有表面的互连结构，与表面相邻布置的多个纳米管的方法和设备，以及邻近表面设置并且基本上包括纳米管的金属层。组件可以包括所描述的装置的第一实施例，并且还可以包括第二实施例，物理地和电耦合到第一实施例中的至少一个。

9. 发明授权

US08387240B2 Methods for making multi-chip packaging using an interposer 有权
标题翻译：使用插入片进行多芯片封装的方法
公开(公告)号：US08387240B2
公开(公告)日：2013-03-05
申请号：US12955816
申请日：2010-11-29
申请人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
发明人： Sriram Muthukumar , Raul Mancera , Yoshihiro Tomita , Chi-won Hwang
IPC分类号： H01K3/10
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/147 , H01L25/0655 , H01L2224/81203 , H01L2224/81815 , H01L2924/10253 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49144 , Y10T29/49163 , Y10T29/49165 , H01L2924/00
摘要： In one embodiment, a method includes forming a plurality of vias partially through a body, the vias including sidewalls defined by the body. An electrically insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. The body is thinned through a lower surface and the electrically insulating layer in the vias is exposed. After the thinning, a portion of the electrically insulating layer in the, vias is removed. The body is coupled to a substrate.
摘要翻译：在一个实施例中，一种方法包括通过主体部分地形成多个通孔，通孔包括由身体限定的侧壁。电绝缘层形成在主体的侧壁和上表面上。在通孔和上表面上的绝缘层上形成导电层，导电层限定上表面上的第一金属焊盘和与第一金属焊盘接触的第二金属焊盘，第二金属焊盘具有较密的间距比第一金属垫。在相邻的第一金属焊盘之间和相邻的第二金属焊盘之间形成介电层。身体通过下表面变薄，并且通孔中的电绝缘层被暴露。在变薄之后，去除通孔中的电绝缘层的一部分。主体耦合到基板。

10. 发明授权

US07535099B2 Sintered metallic thermal interface materials for microelectronic cooling assemblies 有权
标题翻译：用于微电子冷却组件的烧结金属热界面材料
公开(公告)号：US07535099B2
公开(公告)日：2009-05-19
申请号：US11528123
申请日：2006-09-26
申请人： Daewoong Suh , Chi-won Hwang
发明人： Daewoong Suh , Chi-won Hwang
IPC分类号： H01L23/373
CPC分类号： H01L23/3736 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15312 , H01L2924/16195 , H01L2924/00 , H01L2224/0401
摘要： A microelectronic cooling assembly and method for fabricating the same are described. In one example, a microelectronic cooling assembly includes a microelectronic device, a heat spreader, and a thermal interface material (TIM) that thermally joins the microelectronic device and heat spreader, the TIM comprising a sintered metallic nanopaste.
摘要翻译：描述了一种微电子冷却组件及其制造方法。在一个示例中，微电子冷却组件包括微电子器件，散热器和热接合微电子器件和散热器的热界面材料（TIM），TIM包含烧结金属纳米糊剂。

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