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    • 1. 发明申请
    • MULTI-CHIP PACKAGING USING AN INTERPOSER SUCH AS A SILICON BASED INTERPOSER WITH THROUGH-SILICON-VIAS
    • 多芯片封装使用插座等作为基于硅的间插器与穿透硅
    • US20110067236A1
    • 2011-03-24
    • US12955816
    • 2010-11-29
    • Sriram MUTHUKUMARRaul MANCERAYoshihiro TOMITAChi-won HWANG
    • Sriram MUTHUKUMARRaul MANCERAYoshihiro TOMITAChi-won HWANG
    • H01K3/10
    • H01L23/49827H01L21/486H01L23/147H01L25/0655H01L2224/81203H01L2224/81815H01L2924/10253Y10T29/49126Y10T29/49128Y10T29/4913Y10T29/49144Y10T29/49163Y10T29/49165H01L2924/00
    • The formation of electronic assemblies, including assemblies having an interposer, are described. In one embodiment, a method includes forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface of the body, the electrically conductive layer defining a first metal pad layer on the upper surface and a second metal pad layer in contact with the first metal pad layer, the second metal pad layer having a denser pitch between adjacent pads than the first metal pad layer. The method also includes forming a dielectric layer between the adjacent metal pads in the first and second pad layers. The method also includes coupling a plurality of elements to the second metal pad layer. After the coupling the elements, the method includes thinning the body through a lower surface and exposing the electrically insulating layer in the vias. The method also includes removing a portion of the electrically insulating layer in the vias, and coupling the electrically conductive layer to a substrate, wherein the body is positioned between the elements and the substrate. Other embodiments are described and claimed.
    • 描述了包括具有插入件的组件的电子组件的形成。 在一个实施例中,一种方法包括形成多个部分延伸通过主体的通孔,通孔包括由主体限定的侧壁。 绝缘层形成在主体的侧壁和上表面上。 导电层形成在通孔的绝缘层上和主体的上表面上,导电层在上表面上限定第一金属焊盘层和与第一金属焊盘层接触的第二金属焊盘层 ,所述第二金属焊盘层在相邻焊盘之间具有比所述第一金属焊盘层更密的间距。 该方法还包括在第一和第二焊盘层中的相邻金属焊盘之间形成电介质层。 该方法还包括将多个元件耦合到第二金属焊盘层。 在耦合这些元件之后,该方法包括通过下表面使本体变薄并暴露通孔中的电绝缘层。 该方法还包括去除通孔中电绝缘层的一部分,以及将导电层耦合到衬底,其中主体位于元件和衬底之间。 描述和要求保护其他实施例。
    • 2. 发明申请
    • MULTI-CHIP PACKAGING USING AN INTERPOSER SUCH AS A SILICON BASED INTERPOSER WITH THROUGH-SILICON-VIAS
    • 多芯片封装使用插座等作为基于硅的间插器与穿透硅
    • US20080295325A1
    • 2008-12-04
    • US11755735
    • 2007-05-30
    • Sriram MuthukumarRaul ManceraYoshihiro TomitaChi-won Hwang
    • Sriram MuthukumarRaul ManceraYoshihiro TomitaChi-won Hwang
    • H05K3/36
    • H01L23/49827H01L21/486H01L23/147H01L25/0655H01L2224/81203H01L2224/81815H01L2924/10253Y10T29/49126Y10T29/49128Y10T29/4913Y10T29/49144Y10T29/49163Y10T29/49165H01L2924/00
    • The formation of electronic assemblies, including assemblies having an interposer, are described. In one embodiment, a method includes forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface of the body, the electrically conductive layer defining a first metal pad layer on the upper surface and a second metal pad layer in contact with the first metal pad layer, the second metal pad layer having a denser pitch between adjacent pads than the first metal pad layer. The method also includes forming a dielectric layer between the adjacent metal pads in the first and second pad layers. The method also includes coupling a plurality of elements to the second metal pad layer. After the coupling the elements, the method includes thinning the body through a lower surface and exposing the electrically insulating layer in the vias. The method also includes removing a portion of the electrically insulating layer in the vias, and coupling the electrically conductive layer to a substrate, wherein the body is positioned between the elements and the substrate. Other embodiments are described and claimed.
    • 描述了包括具有插入件的组件的电子组件的形成。 在一个实施例中,一种方法包括形成多个部分延伸通过主体的通孔,通孔包括由主体限定的侧壁。 绝缘层形成在主体的侧壁和上表面上。 导电层形成在通孔的绝缘层上和主体的上表面上,导电层在上表面上限定第一金属焊盘层和与第一金属焊盘层接触的第二金属焊盘层 ,所述第二金属焊盘层在相邻焊盘之间具有比所述第一金属焊盘层更密的间距。 该方法还包括在第一和第二焊盘层中的相邻金属焊盘之间形成电介质层。 该方法还包括将多个元件耦合到第二金属焊盘层。 在耦合这些元件之后,该方法包括通过下表面使本体变薄并暴露通孔中的电绝缘层。 该方法还包括去除通孔中电绝缘层的一部分,以及将导电层耦合到衬底,其中本体位于元件和衬底之间。 描述和要求保护其他实施例。