专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07528042B2 Method for fabricating semiconductor devices having dual gate oxide layer 有权
标题翻译：制造具有双栅氧化层的半导体器件的方法
公开(公告)号：US07528042B2
公开(公告)日：2009-05-05
申请号：US11477090
申请日：2006-06-28
申请人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
发明人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/2236 , H01L21/28202 , H01L21/3144 , H01L21/823481 , H01L29/518
摘要： A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.
摘要翻译：一种形成双栅极氧化层的方法，包括以下步骤：a）在半导体衬底上形成栅极氧化层; 和b）通过执行去耦等离子体处理来增加栅极氧化物层的一部分的厚度。额外的热处理不是必需的，因为双栅极氧化物层由解耦的等离子体形成。此外，由于硅衬底没有被损坏，所以可以确保半导体器件的沟道特性。此外，由于在没有额外的沟道离子注入的情况下单元区域中的阈值电压增加，所以可以提高半导体器件的电特性。

2. 发明授权

US07157339B2 Method for fabricating semiconductor devices having dual gate oxide layers 有权
标题翻译：制造具有双栅氧化层的半导体器件的方法
公开(公告)号：US07157339B2
公开(公告)日：2007-01-02
申请号：US10292296
申请日：2002-11-12
申请人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
发明人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/2236 , H01L21/28202 , H01L21/3144 , H01L21/823481 , H01L29/518
摘要： A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.
摘要翻译：一种形成双栅极氧化层的方法，包括以下步骤：a）在半导体衬底上形成栅极氧化层; 和b）通过执行去耦等离子体处理来增加栅极氧化物层的一部分的厚度。额外的热处理不是必需的，因为双栅极氧化物层由解耦的等离子体形成。此外，由于硅基板没有被损坏，所以可以确保半导体器件的沟道特性。此外，由于在没有额外的沟道离子注入的情况下单元区域中的阈值电压增加，所以可以提高半导体器件的电特性。

3. 发明申请

US20060246669A1 Method for fabricating semiconductor devices having dual gate oxide layer 有权
公开(公告)号：US20060246669A1
公开(公告)日：2006-11-02
申请号：US11477090
申请日：2006-06-28
申请人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
发明人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/2236 , H01L21/28202 , H01L21/3144 , H01L21/823481 , H01L29/518
摘要： A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.

4. 发明授权

US06664160B2 Gate structure with high K dielectric 有权
标题翻译：具有高K电介质的栅极结构
公开(公告)号：US06664160B2
公开(公告)日：2003-12-16
申请号：US10298564
申请日：2002-11-19
申请人： Dae-Gyu Park , Heung-Jae Cho
发明人： Dae-Gyu Park , Heung-Jae Cho
IPC分类号： H01L2362
CPC分类号： H01L29/517 , C23C16/405 , H01L21/28185 , H01L21/28194 , H01L21/31604 , H01L29/66545
摘要： A method for forming a gate structure beginning with a semiconductor substrate provided with an isolation region formed therein. An HfO2 layer and a conductive layer are formed on the semiconductor substrate, subsequently. The conductive layer and the HfO2 layer are patterned into the gate structure. By utilizing an HfO2 layer as a gate dielectric, an effective K of the gate dielectric can be controlled to within 18 to 25. In addition, by employing a CVD method for forming the HfO2 layer, it is possible to obtain a high K gate dielectric with excellent leakage current characteristic as well as a low interface state with both a gate electrode and a semiconductor substrate.
摘要翻译：一种形成栅极结构的方法，从形成有隔离区域的半导体衬底开始。随后在半导体衬底上形成HfO 2层和导电层。将导电层和HfO 2层图案化成栅极结构。通过使用HfO 2层作为栅极电介质，可以将栅极电介质的有效K控制在18〜25的范围内。此外，通过采用CVD法形成HfO 2层，可以获得高K栅极电介质具有优异的漏电流特性以及与栅电极和半导体衬底两者的低接口状态。

5. 发明授权

US06511875B2 Method for making high K dielectric gate for semiconductor device 有权
标题翻译：制造半导体器件的高K电介质栅的方法
公开(公告)号：US06511875B2
公开(公告)日：2003-01-28
申请号：US09883188
申请日：2001-06-19
申请人： Dae-Gyu Park , Heung-Jae Cho
发明人： Dae-Gyu Park , Heung-Jae Cho
IPC分类号： H01L218242
CPC分类号： H01L29/517 , C23C16/405 , H01L21/28185 , H01L21/28194 , H01L21/31604 , H01L29/66545
摘要： A method for forming a gate structure beginning with a semiconductor substrate provided with an isolation region formed therein. An HfO2 layer and a conductive layer are formed on the semiconductor substrate, subsequently. The conductive layer and the HfO2 layer are patterned into the gate structure. By utilizing an HfO2 layer as a gate dielectric, an effective K of the gate dielectric can be controlled to within 18 to 25. In addition, by employing a CVD method for forming the HfO2 layer, it is possible to obtain a high K gate dielectric with excellent leakage current characteristic as well as a low interface state with both a gate electrode and a semiconductor substrate.
摘要翻译：一种形成栅极结构的方法，从形成有隔离区域的半导体衬底开始。随后在半导体衬底上形成HfO 2层和导电层。将导电层和HfO 2层图案化成栅极结构。通过使用HfO 2层作为栅极电介质，可以将栅极电介质的有效K控制在18〜25的范围内。此外，通过采用CVD法形成HfO 2层，可以获得高K栅极电介质具有优异的漏电流特性以及与栅电极和半导体衬底两者的低接口状态。

6. 发明授权

US08643061B2 Structure of high-K metal gate semiconductor transistor 有权
标题翻译：高K金属栅半导体晶体管的结构
公开(公告)号：US08643061B2
公开(公告)日：2014-02-04
申请号：US12908024
申请日：2010-10-20
申请人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
发明人： Haizhou Yin , Dae-Gyu Park , Oleg Gluschenkov , Zhijiong Luo , Dominic Schepis , Jun Yuan
IPC分类号： H01L29/66
CPC分类号： H01L21/84 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/1054 , H01L29/66651 , H01L29/78
摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.
摘要翻译：提供半导体结构。该结构包括直接形成在应变硅层的顶部上的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是通过一层硅 - 锗（SiGe）。应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。还提供了形成半导体结构的方法。

7. 发明授权

US08557652B2 Application of cluster beam implantation for fabricating threshold voltage adjusted FETs 失效
公开(公告)号：US08557652B2
公开(公告)日：2013-10-15
申请号：US13608422
申请日：2012-09-10
申请人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
发明人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

8. 发明申请

US20130019944A1 METHOD OF STABILIZING HYDROGENATED AMORPHOUS SILICON AND AMORPHOUS HYDROGENATED SILICON ALLOYS 有权
公开(公告)号：US20130019944A1
公开(公告)日：2013-01-24
申请号：US13188214
申请日：2011-07-21
申请人： Bahman Hekmatshoar-Tabari , Marinus Hopstaken , Dae-Gyu Park , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
发明人： Bahman Hekmatshoar-Tabari , Marinus Hopstaken , Dae-Gyu Park , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L31/0376
CPC分类号： H01L31/03762 , H01L31/02167 , H01L31/075 , H01L31/1864 , H01L31/202 , Y02E10/548 , Y02P70/521
摘要： A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.

9. 发明申请

US20120187502A1 APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS 有权
标题翻译：聚束光束植入用于制造阈值电压调节FET的应用
公开(公告)号：US20120187502A1
公开(公告)日：2012-07-26
申请号：US13432716
申请日：2012-03-28
申请人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
发明人： Oleg Gluschenkov , Dae-Gyu Park , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823857
摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.
摘要翻译：提供了包括高k栅介质材料的半导体结构，其具有位于距离高k栅极电介质的上表面3nm以内的至少一个表面阈值电压调整区域。所述至少一个表面阈值电压调整区域通过聚束射束注入步骤形成，其中至少一个阈值电压调节杂质直接形成在所述高k栅极电介质内或从上限的阈值电压调节材料驱动，所述材料随后从聚束束植入步骤后的结构。

10. 发明授权

US08030716B2 Self-aligned CMOS structure with dual workfunction 有权
标题翻译：具有双功能功能的自对准CMOS结构
公开(公告)号：US08030716B2
公开(公告)日：2011-10-04
申请号：US12883874
申请日：2010-09-16
申请人： Dae-Gyu Park , Michael P. Chudzik , Vijay Narayanan , Vamsi Paruchuri
发明人： Dae-Gyu Park , Michael P. Chudzik , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L21/70
CPC分类号： H01L21/823842 , H01L21/823857 , H01L29/785
摘要： A method for fabricating a CMOS structure is disclosed. The method includes the blanket disposition of a high-k gate insulator layer in an NFET device and in a PFET device, and the implementation of a gate metal layer over the NFET device. This is followed by a blanket disposition of an Al layer over both the NFET device and the PFET device. The method further involves a blanket disposition of a shared gate metal layer over the Al layer. When the PFET device is exposed to a thermal annealing, the high-k dielectric oxidizes the Al layer, thereby turning the Al layer into a PFET interfacial control layer, while in the NFET device the Al becomes a region of the metal gate.
摘要翻译：公开了一种用于制造CMOS结构的方法。该方法包括在NFET器件和PFET器件中的高k栅极绝缘体层的覆盖布置以及NFET器件上的栅极金属层的实现。之后是在NFET器件和PFET器件上的Al层的覆盖布置。该方法还包括在Al层上共享的栅极金属层的布置布置。当PFET器件暴露于热退火时，高k电介质氧化Al层，从而将Al层转变为PFET界面控制层，而在NFET器件中，Al成为金属栅极的一个区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式