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1. 发明授权

US06975547B2 Flash memory devices that support efficient memory locking operations and methods of operating flash memory devices 有权
标题翻译：支持高效内存锁定操作的闪存设备和操作闪存设备的方法
公开(公告)号：US06975547B2
公开(公告)日：2005-12-13
申请号：US10820245
申请日：2004-04-06
申请人： Dae Seok Byeon , Seung-Jae Lee
发明人： Dae Seok Byeon , Seung-Jae Lee
IPC分类号： G06F12/00 , G11C7/24 , G11C16/22 , G11C7/00
CPC分类号： G11C7/24 , G11C16/22
摘要： Flash memory devices include at least one flash memory array and an address compare circuit that is configured to indicate whether an applied row address associated with a first operation (e.g., program, erase) is within or without an unlock area of the at least one flash memory array. A control circuit is also provided. This control circuit is configured to block performance of the first operation on the flash memory array in response to detecting an indication from the address compare circuit that the applied row address is outside the unlock area of the flash memory array.
摘要翻译：闪存设备包括至少一个闪存阵列和地址比较电路，其被配置为指示与第一操作（例如，程序，擦除）相关联的应用行地址是否在至少一个闪存的解锁区域内内存阵列还提供控制电路。响应于检测到来自地址比较电路的指示，所施加的行地址在闪存阵列的解锁区域之外，该控制电路被配置为阻止闪速存储器阵列上的第一操作的性能。

2. 发明授权

US07193878B2 Semiconductor memory device layout including increased length connection lines 失效
标题翻译：半导体存储器件布局包括增加长度的连接线
公开(公告)号：US07193878B2
公开(公告)日：2007-03-20
申请号：US11452798
申请日：2006-06-14
申请人： Pan Suk Kwak , Dae Seok Byeon
发明人： Pan Suk Kwak , Dae Seok Byeon
IPC分类号： G11C5/06 , G11C11/34
CPC分类号： H01L27/10 , G11C5/025 , G11C5/063 , G11C7/18 , G11C8/10 , G11C16/04 , G11C2207/005 , H01L27/105
摘要： An integrated circuit memory device includes a memory cell array including first and second bit lines that extend side-by-side, a plurality of page buffers, a first isolation device electrically coupled to an end of the first bit line, and a second isolation device electrically coupled to an end of the second bit line. The second isolation device is arranged farther from the plurality of page buffers than the first isolation device. A first connection line is electrically coupled at a first end thereof to the first isolation device, and is electrically coupled at a second end thereof to one of the plurality of page buffers. A second connection line is electrically coupled at a first end thereof to the second isolation device, and is electrically coupled at a second end thereof to a farther one of the plurality of page buffers. The second connection line is arranged immediately adjacent to the first bit line.
摘要翻译：集成电路存储器件包括存储单元阵列，其包括并排延伸的第一和第二位线，多个页面缓冲器，电耦合到第一位线的端部的第一隔离器件和第二隔离器件电耦合到第二位线的端部。与第一隔离装置相比，第二隔离装置布置得比多个页缓冲器更远。第一连接线在其第一端处电耦合到第一隔离装置，并且在其第二端处电耦合到多个页缓冲器之一。第二连接线在其第一端处电耦合到第二隔离装置，并且在其第二端处电耦合到多个页面缓冲器中的更远的一个。第二连接线被布置成紧邻第一位线。

3. 发明授权

US07379351B2 Non-volatile semiconductor memory and programming method 有权
标题翻译：非易失性半导体存储器和编程方法
公开(公告)号：US07379351B2
公开(公告)日：2008-05-27
申请号：US11471541
申请日：2006-06-21
申请人： Oh Suk Kwon , Dae Seok Byeon
发明人： Oh Suk Kwon , Dae Seok Byeon
IPC分类号： G11C7/00
CPC分类号： G11C8/10 , G11C16/0483
摘要： In one aspect, a programming method is provided for a non-volatile semiconductor memory device which includes a plurality of electrically programmable and erasable memory cells, and transmission transistors for providing predetermined voltages to the memory cells. The method includes a primary programming process which includes providing a first program voltage to a selected memory cell to program the selected memory cell, a verify read process which includes reading the selected memory cell to verify a programmed status of the selected memory cell resulting from the primary programming process, and a secondary programming process which includes providing a second program voltage to the selected memory cell so as to reprogram the selected memory cell after the verify read process. During the verify read process, the transmission transistors are continuously gated by a boosted voltage generated during the primary programming process. The boosted voltage has a voltage level which is sufficient to provide the first and second program voltages to the memory cell.
摘要翻译：在一个方面，提供一种用于非易失性半导体存储器件的编程方法，该非易失性半导体存储器件包括多个电可编程和可擦除存储器单元，以及用于向存储器单元提供预定电压的传输晶体管。该方法包括主编程过程，其包括向所选择的存储器单元提供第一编程电压以对所选择的存储器单元进行编程;验证读取处理，其包括读取所选择的存储器单元，以验证所选存储器单元的编程状态，主编程处理和辅助编程处理，其包括向所选择的存储器单元提供第二编程电压，以便在验证读取处理之后重新编程所选择的存储器单元。在验证读取过程期间，传输晶体管由主要编程过程中产生的升压电压连续选通。升压电压具有足以向存储单元提供第一和第二编程电压的电压电平。

4. 发明授权

US07272049B2 Nonvolatile semiconductor memory device having uniform operational characteristics for memory cells 有权
标题翻译：具有用于存储单元的均匀操作特性的非易失性半导体存储器件
公开(公告)号：US07272049B2
公开(公告)日：2007-09-18
申请号：US11317300
申请日：2005-12-27
申请人： Dong Ku Kang , Dae Seok Byeon , Young Ho Lim
发明人： Dong Ku Kang , Dae Seok Byeon , Young Ho Lim
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C8/08 , G11C16/08
摘要： A NAND-type nonvolatile semiconductor memory device comprising a cell string that comprises a dummy cell interposed between and connected in series to a string selection transistor and a nonvolatile memory cell is provided. The NAND-type nonvolatile semiconductor memory device further comprises a dummy word line driver adapted to activate a dummy word line to gate the dummy cell.
摘要翻译：一种NAND型非易失性半导体存储器件，包括一个单元串，该单元串包括插入串联选择晶体管和非易失性存储单元之间并串联连接的虚设单元。 NAND型非易失性半导体存储器件还包括一个虚拟字线驱动器，用于激活伪字线以对虚拟单元进行门极化。

5. 发明申请

US20070053218A1 Nonvolatile semiconductor memory device having bitlines extending from cell array in single direction 有权
标题翻译：非易失性半导体存储器件具有从单元阵列沿单向延伸的位线
公开(公告)号：US20070053218A1
公开(公告)日：2007-03-08
申请号：US11513157
申请日：2006-08-31
申请人： Wook Hahn , Dae Seok Byeon
发明人： Wook Hahn , Dae Seok Byeon
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C16/24
摘要： A semiconductor memory device comprises a cell array including a plurality of memory cells. The semiconductor memory device further comprises a plurality of bitlines formed in a bit layer and connected to the plurality of memory cells, wherein the bitlines extend from the cell array along a single direction. A common source line is formed in a common source layer and adapted to provide a predetermined source voltage to the plurality of memory cells. A voltage control block comprising a plurality of voltage control circuits adapted to control the voltage levels of the plurality of bitlines through voltage supply lines formed in a voltage-line metal layer is formed on one side of the cell array.
摘要翻译：半导体存储器件包括包括多个存储单元的单元阵列。半导体存储器件还包括形成在位层中并连接到多个存储器单元的多个位线，其中位线沿着单个方向从单元阵列延伸。公共源极线形成在公共源层中并且适于向多个存储器单元提供预定的源极电压。电压控制块包括多个电压控制电路，其适于通过形成在电压线金属层中的电压供给线来控制多个位线的电压电平，该电压控制电路形成在电池阵列的一侧。

6. 发明申请

US20180108664A1 Memory Devices Using Etching Stop Layers 有权
公开(公告)号：US20180108664A1
公开(公告)日：2018-04-19
申请号：US15604028
申请日：2017-05-24
申请人： Jeong Gil Lee , Jee Yong Kim , Jung Hwan Lee , Dae Seok Byeon , Hyun Seok Lim
发明人： Jeong Gil Lee , Jee Yong Kim , Jung Hwan Lee , Dae Seok Byeon , Hyun Seok Lim
IPC分类号： H01L27/1157 , H01L27/11524 , H01L23/535 , H01L29/06 , H01L29/788 , H01L29/792 , H01L29/423 , G11C16/10 , G11C16/26 , G11C16/08
CPC分类号： H01L27/1157 , G11C16/08 , G11C16/10 , G11C16/26 , H01L23/535 , H01L27/11524 , H01L27/11575 , H01L27/11582 , H01L29/0649 , H01L29/42328 , H01L29/42344 , H01L29/788 , H01L29/792
摘要： A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

7. 发明授权

US07916540B2 Non-volatile memory devices and systems including bad blocks address re-mapped and methods of operating the same 有权
标题翻译：包括坏块的非易失性存储器件和系统重新映射，并且操作它们的方法
公开(公告)号：US07916540B2
公开(公告)日：2011-03-29
申请号：US12122369
申请日：2008-05-16
申请人： Dae Seok Byeon
发明人： Dae Seok Byeon
IPC分类号： G11C11/34
CPC分类号： G11C29/76
摘要： A method of operating a non-volatile memory device included in a memory card can be provided by re-mapping addresses of bad blocks in a first non-volatile MAT in a memory card and re-mapping addresses of bad blocks in a second non-volatile MAT in the memory card, the second non-volatile MAT including blocks that are address mapped with blocks in the first non-volatile MAT. Also a method of scanning a non-volatile memory device for bad blocks can be provided by sequentially scanning blocks in a non-volatile memory device for data indicating that a respective block is a bad block starting at a starting block address that is above a lowermost block address of the non-volatile memory device, wherein the starting block address is based on a yield for the non-volatile memory device.
摘要翻译：可以通过重新映射存储卡中的第一非易失性MAT中的坏块的地址并在第二非易失性存储卡中重新映射坏块的地址来提供操作包括在存储卡中的非易失性存储器件的方法，存储卡中的易失性MAT，第二非易失性MAT包括在第一非易失性MAT中用块映射的地址的块。也可以通过在非易失性存储器件中顺序地扫描块来提供用于扫描不良块的非易失性存储器件的方法，用于指示相应块是从低于最低位置的起始块地址开始的坏块所述非易失性存储器件的块地址，其中所述起始块地址基于所述非易失性存储器件的产量。

8. 发明申请

US20080285347A1 NON-VOLATILE MEMORY DEVICES AND SYSTEMS INCLUDING BAD BLOCKS ADDRESS RE-MAPPED AND METHODS OF OPERATING THE SAME 有权
标题翻译：非易失性存储器件和系统，包括封装地址重新映射及其操作方法
公开(公告)号：US20080285347A1
公开(公告)日：2008-11-20
申请号：US12122369
申请日：2008-05-16
申请人： Dae Seok Byeon
发明人： Dae Seok Byeon
IPC分类号： G11C29/00 , G11C16/08
CPC分类号： G11C29/76
摘要： A method of operating a non-volatile memory device included in a memory card can be provided by re-mapping addresses of bad blocks in a first non-volatile MAT in a memory card and re-mapping addresses of bad blocks in a second non-volatile MAT in the memory card, the second non-volatile MAT including blocks that are address mapped with blocks in the first non-volatile MAT. Also a method of scanning a non-volatile memory device for bad blocks can be provided by sequentially scanning blocks in a non-volatile memory device for data indicating that a respective block is a bad block starting at a starting block address that is above a lowermost block address of the non-volatile memory device, wherein the starting block address is based on a yield for the non-volatile memory device.
摘要翻译：可以通过重新映射存储卡中的第一非易失性MAT中的坏块的地址并在第二非易失性存储卡中重新映射坏块的地址来提供操作包括在存储卡中的非易失性存储器件的方法，存储卡中的易失性MAT，第二非易失性MAT包括在第一非易失性MAT中用块映射的地址的块。也可以通过在非易失性存储器件中顺序地扫描块来提供用于扫描不良块的非易失性存储器件的方法，用于指示相应块是从低于最低位置的起始块地址开始的坏块所述非易失性存储器件的块地址，其中所述起始块地址基于所述非易失性存储器件的产量。

9. 发明授权

US07405978B2 Nonvolatile semiconductor memory device having bitlines extending from cell array in single direction 有权
标题翻译：非易失性半导体存储器件具有从单元阵列沿单向延伸的位线
公开(公告)号：US07405978B2
公开(公告)日：2008-07-29
申请号：US11513157
申请日：2006-08-31
申请人： Wook-Ghee Hahn , Dae Seok Byeon
发明人： Wook-Ghee Hahn , Dae Seok Byeon
IPC分类号： G11C16/24
CPC分类号： G11C5/063 , G11C16/24
摘要： A semiconductor memory device comprises a cell array including a plurality of memory cells. The semiconductor memory device further comprises a plurality of bitlines formed in a bit layer and connected to the plurality of memory cells, wherein the bitlines extend from the cell array along a single direction. A common source line is formed in a common source layer and adapted to provide a predetermined source voltage to the plurality of memory cells. A voltage control block comprising a plurality of voltage control circuits adapted to control the voltage levels of the plurality of bitlines through voltage supply lines formed in a voltage-line metal layer is formed on one side of the cell array.
摘要翻译：半导体存储器件包括包括多个存储单元的单元阵列。半导体存储器件还包括形成在位层中并连接到多个存储器单元的多个位线，其中位线沿着单个方向从单元阵列延伸。公共源极线形成在公共源层中并且适于向多个存储器单元提供预定的源极电压。电压控制块包括多个电压控制电路，其适于通过形成在电压线金属层中的电压供给线来控制多个位线的电压电平，该电压控制电路形成在电池阵列的一侧。

10. 发明授权

US10026746B2 Memory devices using etching stop layers 有权
公开(公告)号：US10026746B2
公开(公告)日：2018-07-17
申请号：US15604028
申请日：2017-05-24
申请人： Jeong Gil Lee , Jee Yong Kim , Jung Hwan Lee , Dae Seok Byeon , Hyun Seok Lim
发明人： Jeong Gil Lee , Jee Yong Kim , Jung Hwan Lee , Dae Seok Byeon , Hyun Seok Lim
IPC分类号： H01L27/115 , H01L27/1157 , H01L27/11524 , H01L23/535 , H01L29/06 , H01L29/788 , H01L29/792 , H01L29/423 , G11C16/10 , G11C16/26 , G11C16/08
摘要： A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

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