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1. 发明申请

US20050210333A1 Performing diagnostic operations upon a data processing apparatus with power down support 有权
标题翻译：对具有断电支持的数据处理设备执行诊断操作
公开(公告)号：US20050210333A1
公开(公告)日：2005-09-22
申请号：US10801131
申请日：2004-03-16
申请人： Conrado Allue , Paul Kimelman , Andrew Swaine , Richard Grisenthwaite
发明人： Conrado Allue , Paul Kimelman , Andrew Swaine , Richard Grisenthwaite
IPC分类号： G01R31/28 , G06F1/32 , G06F11/00 , G06F11/22 , G06F11/30 , H01L21/822 , H01L27/04
CPC分类号： G06F11/2236
摘要： A system-on-chip integrated circuit 2 is provided with multiple data processing circuits 4, 6, 8 each with an associated diagnostic interface circuit 16, 18, 20 connected via a diagnostic transaction bus 14 to a diagnostic transaction master circuit 12. The diagnostic master transaction circuit 12 issues diagnostic transaction requests to the diagnostic interface circuits 16, 18, 20. If the associated data processing circuits 4, 6, 8 are powered-down, or otherwise non responsive, then the diagnostic interface circuit 16, 18, 20 returns a diagnostic bus transaction error signal to the diagnostic transaction master circuit 12. A sticky-bit latch 30 within each diagnostic interface circuit 16, 18, 20 serves to record a power-down event and force generation of the diagnostic bus transaction error signal until that sticky bit is cleared by the diagnostic mechanisms. This ensure the diagnostic mechanisms are made aware of the power-down event so they may take any appropriate remedial action that might be necessary as a result of that power-down event.
摘要翻译：系统级芯片集成电路2具有多个数据处理电路4,6,8，每个数据处理电路具有通过诊断事务总线14连接到诊断事务主电路12的相关联的诊断接口电路16,18,20。诊断主交易电路12向诊断接口电路16,18,20发出诊断事务请求。如果相关联的数据处理电路4,6,8被断电或以其他方式不响应，则诊断接口电路16,18,20将诊断总线事务错误信号返回给诊断事务主电路12。每个诊断接口电路16,18,20内的粘滞锁存器30用于记录诊断总线事务错误信号的掉电事件和强制产生，直到诊断机构清除该粘滞位。这样可以确保诊断机制能够意识到掉电事件，因此可能会由于断电事件而采取任何必要的补救措施。

2. 发明申请

US20050210328A1 Forced diagnostic entry upon power-up 审中-公开
标题翻译：上电时强制诊断输入
公开(公告)号：US20050210328A1
公开(公告)日：2005-09-22
申请号：US10801136
申请日：2004-03-16
申请人： Conrado Allue , Paul Kimelman , Andrew Swaine , Richard Grisenthwaite
发明人： Conrado Allue , Paul Kimelman , Andrew Swaine , Richard Grisenthwaite
IPC分类号： G06F11/00 , G06F11/07 , G06F11/273
CPC分类号： G06F11/2733 , G06F11/079
摘要： A data processing system 2 is described having a central processing unit 4 and a diagnostic mechanism 10. The central processing unit 4 is switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unit 4 resumes into the normal operation mode, execution of program instructions is inhibited by the diagnostic mechanism 10 to allow the diagnostic mechanism to be appropriately programmed such that the immediate power-up code and operations can be properly diagnosed. The requirement to prevent program instruction execution on power-up is programmed by writing to a latch 16 within the diagnostic mechanism 10 prior to the power-down. The prevention of program execution may be achieved, for example, by generation of a halt request or by extending the time period for which the central processing unit 4 is held in reset following power-up.
摘要翻译：描述了具有中央处理单元4和诊断机构10的数据处理系统2。中央处理单元4可切换到掉电模式，从而可以恢复正常操作模式。当中央处理单元4恢复到正常操作模式时，诊断机构10禁止程序指令的执行，以允许对诊断机构进行适当的编程，使得立即上电代码和操作能被正确诊断。通过在断电之前写入诊断机构10内的锁存器16来编程防止上电时程序指令执行的要求。程序执行的防止可以例如通过产生停止请求或通过在上电之后将中央处理单元4保持在复位的时间段来实现。

3. 发明申请

US20050210327A1 Diagnostic mechanisms within multi processing systems 有权
标题翻译：多处理系统中的诊断机制
公开(公告)号：US20050210327A1
公开(公告)日：2005-09-22
申请号：US10801132
申请日：2004-03-16
申请人： Conrado Allue , Paul Kimelman , Andrew Swaine , Michael Williams
发明人： Conrado Allue , Paul Kimelman , Andrew Swaine , Michael Williams
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/366 , G06F11/0724 , G06F11/079
摘要： Within a system-on-chip device 2 having multiple processing circuits 4, 6, 8, one processing circuit 4 may serve to perform diagnostic operations upon another processing circuit 8 by accessing diagnostic data relating to that other circuit. Thus, one processor may, for example, control and perform halting mode type diagnostic or code profiling upon another.
摘要翻译：在具有多个处理电路4,6,8的片上系统装置2中，一个处理电路4可用于通过访问与该另一电路有关的诊断数据来对另一处理电路8执行诊断操作。因此，一个处理器可以例如控制并执行停止模式类型诊断或代码分析。

4. 发明申请

US20050246585A1 Forced diagnostic entry upon power-up 有权
标题翻译：上电时强制诊断输入
公开(公告)号：US20050246585A1
公开(公告)日：2005-11-03
申请号：US11085263
申请日：2005-03-22
申请人： Conrado Blasco Allue , Paul Kimelman , Andrew Swaine , Richard Grisenthwaite
发明人： Conrado Blasco Allue , Paul Kimelman , Andrew Swaine , Richard Grisenthwaite
IPC分类号： G06F11/00 , G06F11/07 , G06F11/273
CPC分类号： G06F11/079 , G06F11/2733
摘要： A data processing system 2 is described having a central processing unit 4 and a diagnostic mechanism 10. The central processing unit 4 is switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unit 4 resumes into the normal operation mode, execution of program instructions is inhibited by the diagnostic mechanism 10 to allow the diagnostic mechanism to be appropriately programmed such that the immediate power-up code and operations can be properly diagnosed. The requirement to prevent program instruction execution on power-up is programmed by writing to a latch 16 within the diagnostic mechanism 10 prior to the power-down. The prevention of program execution may be achieved, for example, by generation of a halt request or by extending the time period for which the central processing unit 4 is held in reset following power-up.
摘要翻译：描述了具有中央处理单元4和诊断机构10的数据处理系统2.中央处理单元4可切换到能够恢复到正常操作模式的掉电模式。当中央处理单元4恢复到正常操作模式时，诊断机构10禁止程序指令的执行，以允许对诊断机构进行适当的编程，使得立即上电代码和操作能被正确诊断。通过在断电之前写入诊断机构10内的锁存器16来编程防止上电时程序指令执行的要求。程序执行的防止可以例如通过产生停止请求或通过在上电之后将中央处理单元4保持在复位的时间段来实现。

5. 发明申请

US20050034017A1 Cross-triggering of processing devices 有权
标题翻译：交叉触发处理设备
公开(公告)号：US20050034017A1
公开(公告)日：2005-02-10
申请号：US10633363
申请日：2003-08-04
申请人： Cedric Airaud , Nicholas Smith , Paul Kimelman , Ian Field , Man Yiu , David McHale , Andrew Swaine
发明人： Cedric Airaud , Nicholas Smith , Paul Kimelman , Ian Field , Man Yiu , David McHale , Andrew Swaine
IPC分类号： G06F11/28 , G06F9/48 , G06F11/07 , G06F11/27 , G06F11/30 , H05K10/00
CPC分类号： G06F11/366 , G06F11/2242 , G06F11/3632 , G06F11/3636
摘要： A data processing apparatus controls cross-triggering of diagnostic processes on a plurality of processing devices. The data processing apparatus comprises a routing module having a plurality of broadcast channels, one or more of the broadcast channels being operable to indicate the occurrence of a diagnostic event on one or more of the plurality of processing devices. The data processing apparatus also comprises an mapping module associated with a corresponding processing device. The interface module programmably asserts diagnostic event signals from the associated processing device to one or more of the plurality of broadcast channels and programmably retrieves diagnostic events signals from processing devices other than the associated processing device from one or more of the plurality of broadcast channels. The retrieved diagnostic event data is used to facilitate triggering of a diagnostic process on the associated processing device in dependence upon said retrieved diagnostic event data.
摘要翻译：数据处理装置控制多个处理装置上的诊断处理的交叉触发。数据处理装置包括具有多个广播信道的路由模块，一个或多个广播信道可操作以指示在多个处理设备中的一个或多个上发生诊断事件。数据处理装置还包括与对应的处理装置相关联的映射模块。接口模块可编程地将来自相关联的处理设备的诊断事件信号断言成多个广播信道中的一个或多个，并且可编程地从多个广播信道中的一个或多个处理装置处理除相关联的处理设备之外的处理设备的诊断事件信号。所检索的诊断事件数据用于根据所检索的诊断事件数据来便利触发关联处理设备上的诊断过程。

6. 发明申请

US20060224866A1 Selecting subroutine return mechanisms 有权
标题翻译：选择子程序返回机制
公开(公告)号：US20060224866A1
公开(公告)日：2006-10-05
申请号：US11092984
申请日：2005-03-30
申请人： Richard Grisenthwaite , Paul Kimelman , David Seal
发明人： Richard Grisenthwaite , Paul Kimelman , David Seal
IPC分类号： G06F9/44
CPC分类号： G06F9/3016 , G06F9/30054 , G06F9/322 , G06F9/4486
摘要： Following execution of a subroutine, a return instruction is executed having an address as an input operand thereto. This input operand is compared with one or more predetermined values to detect a match and the return instruction response is selected in dependence upon whether or not a match is detected. Thus, the return address value can be used to invoke differing return instruction responses, such as an exception return response or a procedure return response. The one or more predetermined addresses may be conveniently allocated to the highest memory addresses within the memory map.
摘要翻译：在执行子程序之后，执行具有作为其输入操作数的地址的返回指令。将该输入操作数与一个或多个预定值进行比较以检测匹配，并且根据是否检测到匹配来选择返回指令响应。因此，返回地址值可以用于调用不同的返回指令响应，例如异常返回响应或过程返回响应。可以方便地将一个或多个预定地址分配给存储器映射内的最高存储器地址。

7. 发明申请

US20060149911A1 DATA PROCESSING APPARATUS HAVING MEMORY PROTECTION UNIT 有权
标题翻译：具有记忆保护单元的数据处理装置
公开(公告)号：US20060149911A1
公开(公告)日：2006-07-06
申请号：US11028501
申请日：2005-01-04
申请人： Paul Kimelman , Richard Grisenthwaite , David Seal
发明人： Paul Kimelman , Richard Grisenthwaite , David Seal
IPC分类号： G06F12/14
CPC分类号： G06F12/1441
摘要： A data processor (100) has a memory operable to store data values; a memory protection unit (130) operable to associate memory attributes with portions of said memory and to identify a plurality of memory regions corresponding to respective address ranges of said memory. The memory protection unit is operable to associate with at least one of the plurality of memory regions (150) a respective memory region specifier comprising an attributes field (230) for defining a set of memory attributes associated with said memory region and a sub-region field (240) for holding a sub-region membership value. The sub-region membership value specifies, for each of a plurality of sub-regions of the memory region, whether respective sub-regions (160-1 to 160-8) are member sub-regions or non-member sub-regions such that said memory attributes are applied to said member sub-regions but are not applied to said non-member sub-regions.
摘要翻译：数据处理器（100）具有可操作以存储数据值的存储器; 存储器保护单元（130），其可操作以将存储器属性与所述存储器的部分相关联，并且识别对应于所述存储器的相应地址范围的多个存储器区域。存储器保护单元可操作以将多个存储器区域（150）中的至少一个与相应的存储器区域说明符相关联，该存储器区域说明符包括用于定义与所述存储器区域相关联的一组存储器属性的属性字段（230）和子区域用于保存子区域成员值的字段（240）。子区域成员关系值针对存储区域的多个子区域中的每一个指定各个子区域（160-1至160-8）是否是成员子区域或非成员子区域，使得所述存储器属性被应用于所述成员子区域，但不应用于所述非成员子区域。

8. 发明申请

US20050177667A1 Interrupt priority control within a nested interrupt system 有权
标题翻译：嵌套中断系统中的中断优先级控制
公开(公告)号：US20050177667A1
公开(公告)日：2005-08-11
申请号：US10775334
申请日：2004-02-11
申请人： Paul Kimelman , Ian Field , Richard Grisenthwaite
发明人： Paul Kimelman , Ian Field , Richard Grisenthwaite
IPC分类号： G06F9/46 , G06F9/48 , G06F13/24
CPC分类号： G06F9/4818
摘要： A data processing system 2 having a nested interrupt controller 24 supports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly programmable) whilst the system is running. In order to prevent problems associated with priority inversions within nested interrupts, the nested interrupt controller when considering whether a pending interrupt should pre-empt existing active interrupts, compares the priority of the pending interrupt with the highest priority of any of the currently active interrupts that are nested together.
摘要翻译：具有嵌套中断控制器24的数据处理系统2支持嵌套的活动中断。与系统正在运行时，与不同中断相关联的优先级别是可改变的（可能是可编程的）。为了防止在嵌套中断中与优先级颠倒相关的问题，嵌套中断控制器在考虑暂挂中断是否应该预先占用现有的活动中断时，将待处理中断的优先级与任何当前活动中断的最高优先级进行比较，嵌套在一起

9. 发明申请

US20050268001A1 Management of polling loops in a data processing apparatus 有权
标题翻译：管理数据处理设备中的轮询循环
公开(公告)号：US20050268001A1
公开(公告)日：2005-12-01
申请号：US11032226
申请日：2005-01-11
申请人： Paul Kimelman , Richard Grisenthwaite
发明人： Paul Kimelman , Richard Grisenthwaite
IPC分类号： G06F1/32 , G06F9/52 , G06F13/10 , G06F13/24 , G06F15/80 , H04K1/00
CPC分类号： G06F13/24 , G06F1/3228
摘要： A data processing apparatus and method are provided for managing polling loops. The data processing apparatus comprises a main processing unit and a subsidiary processing unit operable to perform a task on behalf of the main processing unit. The subsidiary processing unit is operable to set a completion field when the task has been completed and the main processing unit is operable to poll the completion field in order to determine whether the task has been completed. If on polling the completion field a threshold number of times the main processing unit determines that the task has not been completed, the main processing unit is operable to enter a power saving mode. The subsidiary processing unit is operable, when the task has been completed, to cause a notification to be issued on a path interconnecting the main processing unit and the subsidiary processing unit. The main processing unit is arranged, upon receipt of the notification to exit the power saving mode. This provides a particularly efficient technique for managing a polling loop within the data processing apparatus.
摘要翻译：提供了一种用于管理轮询循环的数据处理装置和方法。数据处理装置包括主处理单元和辅助处理单元，可操作以代表主处理单元执行任务。辅助处理单元可操作以在任务完成时设置完成字段，并且主处理单元可操作地轮询完成字段以便确定任务是否已经完成。如果在轮询完成字段时，主处理单元确定任务尚未完成的阈值次数，则主处理单元可操作以进入省电模式。当完成任务时，辅助处理单元可操作地在连接主处理单元和辅助处理单元的路径上发出通知。主处理单元在接收到退出省电模式的通知时被布置。这提供了一种用于管理数据处理装置内的轮询循环的特别有效的技术。

10. 发明申请

US20070266374A1 Stack memory selection upon exception in a data processing system 有权
标题翻译：在数据处理系统中的异常堆栈存储器选择
公开(公告)号：US20070266374A1
公开(公告)日：2007-11-15
申请号：US11431926
申请日：2006-05-11
申请人： Richard Grisenthwaite , Paul Kimelman , David Seal , David Rusling
发明人： Richard Grisenthwaite , Paul Kimelman , David Seal , David Rusling
IPC分类号： G06F9/44
CPC分类号： G06F9/4812 , G06F9/3861 , G06F9/462
摘要： A data processor 2 has privilege levels associated with it including a user level and a privileged level. The processor 2 also has multiple stack memories which can be used including one or more process stacks, a main stack and a deep stack. The stack memory to be used is de-coupled from the privilege level. An activation level state variable tracking the number of pending exceptions is held by the processor and used to modify which stack memory stores pending state values when an exception occurs. If the system is at a base level of activation, corresponding to currently no pending exceptions, then when an exception occurs the current state data is saved on the process stack with the main stack being available for the exception handling code. Particular exceptions can be flagged as requiring use of a deep stack rather than either the process stack or the main stack. If the system is not at the base level of activation, then the main stack is used to save state variables when an exception occurs rather than the process stack.
摘要翻译：数据处理器2具有与其相关联的特权级别，其包括用户级别和特权级别。处理器2还具有可以使用的多个堆栈存储器，包括一个或多个处理堆栈，主堆栈和深堆栈。要使用的堆栈内存从特权级别去耦合。跟踪待处理异常的数量的激活级状态变量由处理器保存，并用于修改哪个堆栈存储器在发生异常时存储待处理的状态值。如果系统处于激活的基本级别，对应于当前没有挂起的异常，则当发生异常时，当前状态数据保存在进程堆栈中，主堆栈可用于异常处理代码。可以将特殊异常标记为需要使用深栈，而不是使用进程堆栈或主堆栈。如果系统不在激活的基本级别，则主堆栈用于在异常发生时保存状态变量而不是进程堆栈。

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