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1. 发明申请

US20050034017A1 Cross-triggering of processing devices 有权
标题翻译：交叉触发处理设备
公开(公告)号：US20050034017A1
公开(公告)日：2005-02-10
申请号：US10633363
申请日：2003-08-04
申请人： Cedric Airaud , Nicholas Smith , Paul Kimelman , Ian Field , Man Yiu , David McHale , Andrew Swaine
发明人： Cedric Airaud , Nicholas Smith , Paul Kimelman , Ian Field , Man Yiu , David McHale , Andrew Swaine
IPC分类号： G06F11/28 , G06F9/48 , G06F11/07 , G06F11/27 , G06F11/30 , H05K10/00
CPC分类号： G06F11/366 , G06F11/2242 , G06F11/3632 , G06F11/3636
摘要： A data processing apparatus controls cross-triggering of diagnostic processes on a plurality of processing devices. The data processing apparatus comprises a routing module having a plurality of broadcast channels, one or more of the broadcast channels being operable to indicate the occurrence of a diagnostic event on one or more of the plurality of processing devices. The data processing apparatus also comprises an mapping module associated with a corresponding processing device. The interface module programmably asserts diagnostic event signals from the associated processing device to one or more of the plurality of broadcast channels and programmably retrieves diagnostic events signals from processing devices other than the associated processing device from one or more of the plurality of broadcast channels. The retrieved diagnostic event data is used to facilitate triggering of a diagnostic process on the associated processing device in dependence upon said retrieved diagnostic event data.
摘要翻译：数据处理装置控制多个处理装置上的诊断处理的交叉触发。数据处理装置包括具有多个广播信道的路由模块，一个或多个广播信道可操作以指示在多个处理设备中的一个或多个上发生诊断事件。数据处理装置还包括与对应的处理装置相关联的映射模块。接口模块可编程地将来自相关联的处理设备的诊断事件信号断言成多个广播信道中的一个或多个，并且可编程地从多个广播信道中的一个或多个处理装置处理除相关联的处理设备之外的处理设备的诊断事件信号。所检索的诊断事件数据用于根据所检索的诊断事件数据来便利触发关联处理设备上的诊断过程。

2. 发明申请

US20060242501A1 Communication interface for diagnostic circuits of an integrated circuit 有权
标题翻译：集成电路诊断电路的通讯接口
公开(公告)号：US20060242501A1
公开(公告)日：2006-10-26
申请号：US11343210
申请日：2006-01-31
申请人： Paul Kimelman , Edmond Ashfield , Thomas Houlihane , Ian Field
发明人： Paul Kimelman , Edmond Ashfield , Thomas Houlihane , Ian Field
IPC分类号： G01R31/28
CPC分类号： G06F13/4282 , G01R31/31713 , G01R31/318572
摘要： An integrated circuit is provided with diagnostic circuitry, such as serial scan chains or debug bus access circuits, with which communication is established using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals.
摘要翻译：集成电路设置有诸如串行扫描链或调试总线访问电路的诊断电路，通过使用与到外部诊断装置的双向串行链路耦合的接口电路来建立通信。双向串行链路携带数据和控制信号。

3. 发明授权

US07080178B2 Interrupt pre-emption and ordering within a data processing system 有权
标题翻译：在数据处理系统中中断优先和排序
公开(公告)号：US07080178B2
公开(公告)日：2006-07-18
申请号：US10773452
申请日：2004-02-09
申请人： Paul Kimelman , Ian Field
发明人： Paul Kimelman , Ian Field
IPC分类号： G06F13/24 , G06F13/26
CPC分类号： G06F13/26
摘要： A data processing system nested interrupt controller 24 responsive to priority level values 28, 30 associated with respective interrupt handling programs to control the execution of those interrupt handling programs. The priority level values have a first portion 28 which controls whether or not a pending interrupt handling program will pre-empt an already active interrupt handling program and a second portion 30 which controls which of a plurality of pending interrupt handling programs will be executed next when they share the same value for the first portion of their priority level value.
摘要翻译：数据处理系统嵌套中断控制器24响应于与各个中断处理程序相关联的优先级值28,30，以控制这些中断处理程序的执行。优先级值具有第一部分28，该第一部分28控制待决中断处理程序是否将预先占用已经活动的中断处理程序，而第二部分30控制下一个将执行多个待处理的中断处理程序中的哪一个，它们对于其优先级值的第一部分共享相同的值。

4. 发明申请

US20050177691A1 Access to bit values within data words stored in a memory 有权
标题翻译：访问存储在存储器中的数据字中的位值
公开(公告)号：US20050177691A1
公开(公告)日：2005-08-11
申请号：US10773453
申请日：2004-02-09
申请人： Paul Kimelman , Ian Field
发明人： Paul Kimelman , Ian Field
IPC分类号： G06F9/34 , G06F12/02 , G06F12/04 , G06F12/08 , G06F12/10
CPC分类号： G06F12/04
摘要： A data processing system 2 has a base data address region 24 and a bit-band data address region 28. Memory accesses to the bit-band data address region 28 are converted into memory accesses to the base data address region 24. In the process of this conversion specific bits within the base data address region 24 are picked out for access whether that be via a read-modify-write operation or a masked read operation as appropriate. In this way, bit access is provided to data values within the base data address region 24 by addressing specific address locations within the bit-band data address region 28.
摘要翻译：数据处理系统2具有基本数据地址区域24和位带数据地址区域28。对位带数据地址区域28的存储器访问被转换为对基本数据地址区域24的存储器访问。在该转换过程中，基本数据地址区域24中的特定位被拾取用于存取，无论是通过读取 - 修改 - 写入操作还是适当的掩蔽读取操作。以这种方式，通过寻址位数据地址区域28内的特定地址位置，向基数据地址区域24内的数据值提供位访问。

5. 发明授权

US08112560B2 Controlling complex non-linear data transfers 有权
标题翻译：控制复杂的非线性数据传输
公开(公告)号：US08112560B2
公开(公告)日：2012-02-07
申请号：US12805913
申请日：2010-08-24
申请人： Paul Kimelman , Edmond John Simon Ashfield , Steven Richard Mellor , Ian Field
发明人： Paul Kimelman , Edmond John Simon Ashfield , Steven Richard Mellor , Ian Field
IPC分类号： G06F13/28 , G06F13/36
CPC分类号： G06F13/28
摘要： A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.
摘要翻译：公开了一种用于控制多个数据源与多个数据目的地之间的数据传输的直接存储器存取控制器。多个数据源和数据目的地经由多个通道与直接存储器访问控制器通信，直接存储器访问控制器还与存储器和处理器进行通信。存储器存储用于多个通道中的每个通道和处理器的两组控制数据。直接存储器存取控制器响应于从所述多个通道中的一个或从所述处理器接收的数据传输请求，以访问存储在所述存储器中的一组所述对应控制数据，所述直接存储器访问执行所述数据的至少一部分根据所访问的控制数据请求传送。

6. 发明授权

US07243206B2 Method and apparatus for using a RAM memory block to remap ROM access requests 有权
标题翻译：用于使用RAM存储器块重新映射ROM访问请求的方法和装置
公开(公告)号：US07243206B2
公开(公告)日：2007-07-10
申请号：US10412693
申请日：2003-04-14
申请人： Paul Kimelman , Ian Field
发明人： Paul Kimelman , Ian Field
IPC分类号： G06F12/12
CPC分类号： G06F9/342 , G06F9/30181 , G06F12/0638 , G06F2212/2022
摘要： A method and data processing apparatus for remapping selected data access requests issued by a processor for accessing data items stored on a ROM. The method comprises the following steps: storing at least one replacement data item corresponding to at least one data item and different to said at least one data item in a portion of a RAM memory block, said RAM memory block being accessible by said processor, and said portion having been defined for storage of said at least one replacement data item; intercepting a data access request from said processor to said ROM; comparing at least a portion of an address of said intercepted data access request with a stored at least one identifier, said stored at least one identifier identifying an address of at least one data item stored on said ROM, and depending on said comparison either: remapping said data access request to said RAM memory block, such that a replacement data item stored on said memory block is accessed if said comparison indicates said at least a portion of an address to correspond to an address identified by said at least one identifier; or if said comparison indicates said at least a portion of an address not to be an address identified by said at least one stored identifier accessing a data item located at a position corresponding to said address on said ROM.
摘要翻译：一种用于重新映射由处理器发出的用于访问存储在ROM上的数据项的所选择的数据访问请求的方法和数据处理装置。该方法包括以下步骤：在RAM存储器块的一部分中存储至少一个对应于至少一个数据项并且与所述至少一个数据项不同的替换数据项，所述RAM存储块可由所述处理器访问，以及所述部分已经被定义用于存储所述至少一个替换数据项; 截取从所述处理器到所述ROM的数据访问请求; 将所述截取的数据访问请求的地址的至少一部分与存储的至少一个标识符进行比较，所述存储的至少一个标识符识别存储在所述ROM上的至少一个数据项的地址，并且根据所述比较：重新映射所述数据访问请求到所述RAM存储器块，使得如果所述比较指示地址的所述至少一部分对应于由所述至少一个标识符标识的地址，则访问存储在所述存储器块上的替换数据项; 或者如果所述比较指示所述地址的至少一部分不是由所述至少一个存储的标识符识别的地址，其访问位于与所述ROM上的所述地址相对应的位置的数据项。

7. 发明授权

US07607133B2 Interrupt processing control 有权
标题翻译：中断处理控制
公开(公告)号：US07607133B2
公开(公告)日：2009-10-20
申请号：US10775335
申请日：2004-02-11
申请人： Paul Kimelman , Ian Field
发明人： Paul Kimelman , Ian Field
IPC分类号： G06F9/46 , G06F9/44 , G06F3/00 , G06F13/24 , G06F13/26
CPC分类号： G06F9/4818
摘要： A data processing system 2 supporting interrupt handling is provided with an interrupt controller 24. The interrupt controller is responsive to save state data when interrupt processing is commenced by pre-emption of existing processing, whether that be background processing or another interrupt. If a further interrupt is required to be executed immediately after the interrupt which triggered the pre-emption, then the speed with which interrupt processing can be started is advantageously increased if that subsequent interrupt processing is performed without restoring and then resaving the original state data. The interrupts in this arrangement can be considered to be chained together without intervening save and restore operations.
摘要翻译：支持中断处理的数据处理系统2具有中断控制器24.中断控制器响应于通过抢占现有处理开始中断处理时的保存状态数据，无论是后台处理还是另一个中断。如果在触发优先级的中断之后立即执行进一步中断，则如果在不恢复然后重新保存原始状态数据的情况下执行后续中断处理，则有利地增加可以开始中断处理的速度。这种安排的中断可以被认为是链接在一起的，而不需要进行保存和恢复操作。

8. 发明申请

US20080201494A1 Controlling complex non-linear data transfers 有权
标题翻译：控制复杂的非线性数据传输
公开(公告)号：US20080201494A1
公开(公告)日：2008-08-21
申请号：US11707275
申请日：2007-02-16
申请人： Paul Kimelman , Edmond John Simon Ashfield , Steven Richard Mellor , Ian Field
发明人： Paul Kimelman , Edmond John Simon Ashfield , Steven Richard Mellor , Ian Field
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.
摘要翻译：公开了一种用于控制多个数据源与多个数据目的地之间的数据传输的直接存储器存取控制器。多个数据源和数据目的地经由多个通道与直接存储器访问控制器通信，直接存储器访问控制器还与存储器和处理器进行通信。存储器存储用于多个通道中的每个通道和处理器的两组控制数据。直接存储器存取控制器响应于从所述多个通道中的一个或从所述处理器接收的数据传输请求，以访问存储在所述存储器中的一组所述对应控制数据，所述直接存储器访问执行所述数据的至少一部分根据所访问的控制数据请求传送。

9. 发明授权

US07412633B2 Communication interface for diagnostic circuits of an integrated circuit 有权
标题翻译：集成电路诊断电路的通讯接口
公开(公告)号：US07412633B2
公开(公告)日：2008-08-12
申请号：US11343210
申请日：2006-01-31
申请人： Paul Kimelman , Edmond John Simon Ashfield , Thomas Sean Houlihane , Ian Field
发明人： Paul Kimelman , Edmond John Simon Ashfield , Thomas Sean Houlihane , Ian Field
IPC分类号： G01R31/28
CPC分类号： G06F13/4282 , G01R31/31713 , G01R31/318572
摘要： An integrated circuit is provided with diagnostic circuitry, such as serial scan chains or debug bus access circuits, with which communication is established using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals.
摘要翻译：集成电路设置有诸如串行扫描链或调试总线访问电路的诊断电路，通过使用与到外部诊断装置的双向串行链路耦合的接口电路来建立通信。双向串行链路携带数据和控制信号。

10. 发明授权

US07197680B2 Communication interface for diagnostic circuits of an integrated circuit 有权
标题翻译：集成电路诊断电路的通讯接口
公开(公告)号：US07197680B2
公开(公告)日：2007-03-27
申请号：US10417330
申请日：2003-04-17
申请人： Paul Kimelman , Ian Field
发明人： Paul Kimelman , Ian Field
IPC分类号： G01R31/28
CPC分类号： G06F13/4282 , G01R31/31713 , G01R31/318572
摘要： An integrated circuit including diagnostic circuitry having serial scan chains or debug bus access circuits for establishing communication using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals. The serial protocol provides for a pacing signal for indicating to the external diagnostic device when it is ready to receive more data and/or when it has completed a particular diagnostic operation. This provides a self-pacing ability. A training signal generated by the external diagnostic device is detected by the interface circuit on initialization and used to derive sampling point timings.
摘要翻译：一种集成电路，包括具有串行扫描链的诊断电路或用于使用与双向串行链路耦合到外部诊断装置的接口电路建立通信的调试总线访问电路。双向串行链路携带数据和控制信号。串行协议提供了一种起搏信号，用于在外部诊断设备准备好接收更多数据时和/或完成特定的诊断操作时向外部诊断设备指示。这提供了自动起搏功能。由外部诊断装置产生的训练信号在初始化时由接口电路检测并用于导出采样点定时。

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