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1. 发明申请

US20110179215A1 PROGRAMMABLE READ PREAMBLE 有权
标题翻译：可编程阅读前置
公开(公告)号：US20110179215A1
公开(公告)日：2011-07-21
申请号：US12691633
申请日：2010-01-21
申请人： Clifford Alan Zitlaw , Anthony Le
发明人： Clifford Alan Zitlaw , Anthony Le
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/20 , G11C7/1072 , G11C7/20
摘要： The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment.
摘要翻译：主题系统和/或方法涉及能够在制造之后更新前导码模式的高速存储器设备。高速存储器件可以包括闪存模块和RAM模块。 FLASH模块可以包括初始前导码模式，其中在高速存储器的加电期间加载初始前导码模式。 RAM模块可以包括默认前导码模式，其中在高速存储器上电之后加载默认前导码模式。可以通过制造高速存储器或高速存储器的OEM来定义初始前导码模式或默认前导码模式。另外，可以使用基于目标环境的定制前导码模式来更新初始前导码模式或默认前导码模式。

2. 发明申请

US20120066464A1 APPARATUS AND METHOD FOR PROGRAMMABLE READ PREAMBLE 有权
标题翻译：可编程读取前缀的装置和方法
公开(公告)号：US20120066464A1
公开(公告)日：2012-03-15
申请号：US12879936
申请日：2010-09-10
申请人： Clifford Alan Zitlaw , Anthony Le
发明人： Clifford Alan Zitlaw , Anthony Le
IPC分类号： G06F12/00 , G06F12/16
CPC分类号： G06F12/16 , G06F1/12 , G06F11/10 , G08B5/222 , G11C5/066 , G11C7/1006 , G11C7/222 , G11C11/5621 , G11C16/00 , H04L7/04
摘要： A memory device is provided. The memory device includes a preamble memory and a memory controller. The preamble memory is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data. Further, the training pattern is programmable such that the training pattern can be altered at least once subsequent to manufacture of the preamble memory. In response to a read command, the memory controller provides the read preamble stored in the preamble memory, as well as the read data.
摘要翻译：提供存储器件。该存储器件包括前置码存储器和存储器控制器。前导码存储器被布置为存储读取前导码，使得读取前导码包括适合于对准用于读取数据的捕获点的训练模式。此外，训练模式是可编程的，使得训练模式可以在制造前同步码存储器之后至少改变一次。响应于读取命令，存储器控制器提供存储在前导码存储器中的读取前导码以及读取的数据。

3. 发明授权

US09223726B2 Apparatus and method for programmable read preamble with training pattern 有权
标题翻译：具有训练模式的可编程读取前导码的装置和方法
公开(公告)号：US09223726B2
公开(公告)日：2015-12-29
申请号：US12879936
申请日：2010-09-10
申请人： Clifford Alan Zitlaw , Anthony Le
发明人： Clifford Alan Zitlaw , Anthony Le
IPC分类号： G06F3/00 , G06F12/16 , G11C16/00 , G08B5/22 , G06F11/10 , G11C7/22 , H04L7/04 , G06F1/12
CPC分类号： G06F12/16 , G06F1/12 , G06F11/10 , G08B5/222 , G11C5/066 , G11C7/1006 , G11C7/222 , G11C11/5621 , G11C16/00 , H04L7/04
摘要： A memory device is provided. The memory device includes a preamble memory and a memory controller. The preamble memory is arranged to store a read preamble such that the read preamble includes a training pattern that is suitable for aligning a capture point for read data. Further, the training pattern is programmable such that the training pattern can be altered at least once subsequent to manufacture of the preamble memory. In response to a read command, the memory controller provides the read preamble stored in the preamble memory, as well as the read data.
摘要翻译：提供存储器件。该存储器件包括前置码存储器和存储器控制器。前导码存储器被布置为存储读取前导码，使得读取前导码包括适合于对准用于读取数据的捕获点的训练模式。此外，训练模式是可编程的，使得训练模式可以在制造前同步码存储器之后至少改变一次。响应于读取命令，存储器控制器提供存储在前导码存储器中的读取前导码以及读取的数据。

4. 发明授权

US08417874B2 High speed memory having a programmable read preamble 有权
标题翻译：具有可编程读取前置码的高速存储器
公开(公告)号：US08417874B2
公开(公告)日：2013-04-09
申请号：US12691633
申请日：2010-01-21
申请人： Clifford Alan Zitlaw , Anthony Le
发明人： Clifford Alan Zitlaw , Anthony Le
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C7/1072 , G11C7/20
摘要： The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment.
摘要翻译：主题系统和/或方法涉及能够在制造之后更新前导码模式的高速存储器设备。高速存储器件可以包括闪存模块和RAM模块。 FLASH模块可以包括初始前导码模式，其中在高速存储器的加电期间加载初始前导码模式。 RAM模块可以包括默认前导码模式，其中在高速存储器上电之后加载默认前导码模式。可以通过制造高速存储器或高速存储器的OEM来定义初始前导码模式或默认前导码模式。另外，可以使用基于目标环境的定制前导码模式来更新初始前导码模式或默认前导码模式。

5. 发明授权

US08945933B2 Liquid chromatography-mass spectrometry methods for multiplexed detection and quantitation of free amino acids 有权
标题翻译：用于多重检测和定量游离氨基酸的液相色谱 - 质谱法
公开(公告)号：US08945933B2
公开(公告)日：2015-02-03
申请号：US12902908
申请日：2010-10-12
申请人： Anthony Le , Tina Cowan
发明人： Anthony Le , Tina Cowan
IPC分类号： G01N33/00 , G01N24/00 , G01N30/02 , G01N33/68 , G01N30/14 , G01N30/60 , G01N30/72 , G01N30/88
CPC分类号： G01N33/6806 , G01N30/14 , G01N30/6004 , G01N30/7233 , G01N33/6848 , G01N2030/8818 , G01N2500/10 , G01N2800/04 , G01N2800/52 , Y10T436/24
摘要： The present invention provides liquid chromatography-mass spectrometry methods and kits for the specific, sensitive and rapid detection as well as quantitation of free amino acids in samples following High Pressure Liquid Chromatography (HPLC) separation.
摘要翻译：本发明提供用于在高压液相色谱（HPLC）分离后样品中游离氨基酸的特异性，灵敏和快速检测以及定量游离氨基酸的液相色谱 - 质谱法和试剂盒。

6. 发明授权

US07979625B2 SPI bank addressing scheme for memory densities above 128Mb 有权
标题翻译：存储密度高于128Mb的SPI bank寻址方案
公开(公告)号：US07979625B2
公开(公告)日：2011-07-12
申请号：US11945292
申请日：2007-11-27
申请人： Anthony Le , Malcolm Kitchen , Jackson Huang
发明人： Anthony Le , Malcolm Kitchen , Jackson Huang
IPC分类号： G06F13/28
CPC分类号： G06F12/06 , G06F2212/1004 , G06F2212/2022
摘要： Systems and methods of addressing two or more banks of memory utilizing a single-bank serial peripheral interface and an at least three-byte address protocol are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to address one of the memory banks using the three-byte addressing scheme, and to write data to or read data from the addressed bank, and a bank register pointer component coupled to the serial processing component, the pointer component comprising two or more bank register pointers associated with respective memory banks, and configured to select one of the memory banks based on the two or more bank register pointers, wherein the bank register pointer component selects one of the two or more memory banks, and the serial processing component writes data to or reads data from the selected bank of memory according to the three-byte addressing scheme.
摘要翻译：提供了利用单组串行外设接口和至少三字节地址协议来寻址两个或多个存储器组的系统和方法。在一个实施例中，串行外设接口包括串行处理组件，其被配置为使用三字节寻址方案寻址存储器组之一，并将数据写入或从所寻址的存储体读取数据，以及耦合到所述串行处理组件，所述指针组件包括与相应存储体相关联的两个或多个存储体寄存器指针，并且被配置为基于所述两个或多个存储体寄存器指针来选择所述存储器组之一，其中所述存储体寄存器指针组件选择两个或多个存储器组，并且串行处理组件根据三字节寻址方案将数据写入或从所选择的存储器组中读取数据。

7. 发明申请

US20090138694A1 SPI AUTO-BOOT MODE 有权
标题翻译： SPI自动启动模式
公开(公告)号：US20090138694A1
公开(公告)日：2009-05-28
申请号：US11945316
申请日：2007-11-27
申请人： Anthony Le , Jackson Huang
发明人： Anthony Le , Jackson Huang
IPC分类号： G06F15/177
CPC分类号： G06F9/4403
摘要： Systems and methods of detecting an auto-boot mode and booting data from a serial peripheral interface to a processor without the need of a read instruction utilizing a serial peripheral interface having an auto-boot mode detector are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to serially communicate data between the processor and at least two peripherals, and an auto-boot component operably coupled to the serial processing component, comprising an auto-boot mode detector configured to determine whether a boot mode exists based on detecting whether serial input data is received during a predetermined wait state, and configured to selectively boot data to a start address associated with the processor based on the boot mode determination.
摘要翻译：提供了检测自动启动模式并将数据从串行外设接口引导到处理器的系统和方法，而不需要利用具有自动启动模式检测器的串行外围接口的读取指令。在一个实施例中，串行外围设备接口包括被配置为在处理器和至少两个外围设备之间串行传送数据的串行处理组件，以及可操作地耦合到串行处理组件的自动启动组件，包括自动启动模式检测器，基于检测在预定等待状态期间是否接收到串行输入数据，确定是否存在引导模式，并且被配置为基于引导模式确定来选择性地将数据引导到与处理器相关联的起始地址。

8. 发明授权

US07366939B2 Providing precise timing control between multiple standardized test instrumentation chassis 失效
标题翻译：在多个标准化测试仪器底盘之间提供精确的时序控制
公开(公告)号：US07366939B2
公开(公告)日：2008-04-29
申请号：US11196873
申请日：2005-08-03
申请人： Anthony Le , Glen Gomes
发明人： Anthony Le , Glen Gomes
IPC分类号： G06F1/12
CPC分类号： G01R31/31715 , G01R31/31716 , G01R31/31717 , G01R31/31726
摘要： Precise timing control across multiple standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL within each chassis, and by providing these control signals to other chassis. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.
摘要翻译：通过在每个机箱内的PXI_LOCAL上提供多个控制信号，并通过向其他机箱提供这些控制信号，可以获得多个标准化机箱（如PXI）的精确时序控制。最低共通信号（LCM）信号使所有时钟在每个LCM边沿都具有一致的时钟边沿。启动顺序允许测试系统中的所有PXI扩展卡同时启动。一个MATCH线使PIN卡模块能够检查预期的DUT输出，并继续执行本地测试程序或回送并根据DUT输出检查的结果重复本地测试程序的一部分。如果pincard模块中的本地测试程序检测到错误，则测试结束（EOT）线可以使任何一个pincard模块突然结束在所有其他pincard模块中运行的本地测试程序。

9. 发明授权

US07089135B2 Event based IC test system 失效
标题翻译：基于事件的IC测试系统
公开(公告)号：US07089135B2
公开(公告)日：2006-08-08
申请号：US10150777
申请日：2002-05-20
申请人： Rochit Rajsuman , Shigeru Sugamori , Robert F. Sauer , Hiroaki Yamoto , James Alan Turnquist , Bruce R. Parnas , Anthony Le
发明人： Rochit Rajsuman , Shigeru Sugamori , Robert F. Sauer , Hiroaki Yamoto , James Alan Turnquist , Bruce R. Parnas , Anthony Le
IPC分类号： G01R31/00
CPC分类号： G01R31/31813 , G01R31/318307 , G01R31/318342 , G01R31/31917 , G01R31/31919 , G01R31/31928
摘要： An event based test system for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment. The event based test system includes an event memory for storing event data derived directly from simulation of design data for an intended IC in the EDA environment where the event data to denote each event is formed with time index indicating a time length from a predetermined point and an event type indicating a type of change at an event, an event generation unit for generating test vectors based on the event data where waveform of each vector is determined by the event type and a timing of the waveform is determined by accumulating the time index of previous events, and means for supplying test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings.
摘要翻译：一种基于事件的测试系统，用于测试在自动电子设计（EDA）环境下设计的待测IC器件（DUT）。基于事件的测试系统包括事件存储器，用于存储在EDA环境中直接从对于期望的IC的设计数据的模拟得到的事件数据，其中表示每个事件的事件数据形成有指示来自预定点的时间长度的时间索引，指示事件变化类型的事件类型，用于根据事件数据生成测试矢量的事件生成单元，其中由事件类型确定每个矢量的波形，并且通过累积波形的时间指数来确定波形的定时以前的事件，以及用于向DUT提供测试向量并在预定定时评估DUT的响应输出的装置。

10. 发明授权

US06710590B1 Test head Hifix for semiconductor device testing apparatus 失效
标题翻译：测试头Hifix用于半导体器件测试仪器
公开(公告)号：US06710590B1
公开(公告)日：2004-03-23
申请号：US10319110
申请日：2002-12-12
申请人： Niels Markert , Anthony Le , Hiroki Yamoto , Robert Sauer
发明人： Niels Markert , Anthony Le , Hiroki Yamoto , Robert Sauer
IPC分类号： G01R3102
CPC分类号： G01R31/2851
摘要： The present invention is directed to a test head Hifix of a semiconductor device testing apparatus that does not require disassembly for maintenance or repair of the semiconductor device testing apparatus. In one embodiment, the test head Hifix of a semiconductor device testing apparatus includes a plate that resides as the top surface of a test head and on which the assembly, loadboard, socket and DUT are mounted. The plate is attached to the test head in an arrangement that allows the plate along with the assembly, loadboard, socket and DUT to be easily moved without completely disassembling the plate, assembly and loadboard from the test head. In one embodiment, the plate is attached or coupled to the test head by hinges.
摘要翻译：本发明涉及半导体器件测试装置的测试头Hifix，其不需要拆卸用于半导体器件测试装置的维护或修理。在一个实施例中，半导体器件测试装置的测试头Hifix包括作为测试头的顶表面的板，并且其上安装有组件，装载板，插座和DUT。该板以允许板与组件，装载板，插座和DUT一起容易移动的布置附接到测试头，而不会完全拆卸测试头的板，组件和装载板。在一个实施例中，板通过铰链连接或连接到测试头。

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