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    • 1. 发明申请
    • PROGRAMMABLE READ PREAMBLE
    • 可编程阅读前置
    • US20110179215A1
    • 2011-07-21
    • US12691633
    • 2010-01-21
    • Clifford Alan ZitlawAnthony Le
    • Clifford Alan ZitlawAnthony Le
    • G06F12/00G06F12/02
    • G11C16/20G11C7/1072G11C7/20
    • The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment.
    • 主题系统和/或方法涉及能够在制造之后更新前导码模式的高速存储器设备。 高速存储器件可以包括闪存模块和RAM模块。 FLASH模块可以包括初始前导码模式,其中在高速存储器的加电期间加载初始前导码模式。 RAM模块可以包括默认前导码模式,其中在高速存储器上电之后加载默认前导码模式。 可以通过制造高速存储器或高速存储器的OEM来定义初始前导码模式或默认前导码模式。 另外,可以使用基于目标环境的定制前导码模式来更新初始前导码模式或默认前导码模式。
    • 4. 发明授权
    • High speed memory having a programmable read preamble
    • 具有可编程读取前置码的高速存储器
    • US08417874B2
    • 2013-04-09
    • US12691633
    • 2010-01-21
    • Clifford Alan ZitlawAnthony Le
    • Clifford Alan ZitlawAnthony Le
    • G06F12/00
    • G11C16/20G11C7/1072G11C7/20
    • The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment.
    • 主题系统和/或方法涉及能够在制造之后更新前导码模式的高速存储器设备。 高速存储器件可以包括闪存模块和RAM模块。 FLASH模块可以包括初始前导码模式,其中在高速存储器的加电期间加载初始前导码模式。 RAM模块可以包括默认前导码模式,其中在高速存储器上电之后加载默认前导码模式。 可以通过制造高速存储器或高速存储器的OEM来定义初始前导码模式或默认前导码模式。 另外,可以使用基于目标环境的定制前导码模式来更新初始前导码模式或默认前导码模式。
    • 6. 发明授权
    • SPI bank addressing scheme for memory densities above 128Mb
    • 存储密度高于128Mb的SPI bank寻址方案
    • US07979625B2
    • 2011-07-12
    • US11945292
    • 2007-11-27
    • Anthony LeMalcolm KitchenJackson Huang
    • Anthony LeMalcolm KitchenJackson Huang
    • G06F13/28
    • G06F12/06G06F2212/1004G06F2212/2022
    • Systems and methods of addressing two or more banks of memory utilizing a single-bank serial peripheral interface and an at least three-byte address protocol are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to address one of the memory banks using the three-byte addressing scheme, and to write data to or read data from the addressed bank, and a bank register pointer component coupled to the serial processing component, the pointer component comprising two or more bank register pointers associated with respective memory banks, and configured to select one of the memory banks based on the two or more bank register pointers, wherein the bank register pointer component selects one of the two or more memory banks, and the serial processing component writes data to or reads data from the selected bank of memory according to the three-byte addressing scheme.
    • 提供了利用单组串行外设接口和至少三字节地址协议来寻址两个或多个存储器组的系统和方法。 在一个实施例中,串行外设接口包括串行处理组件,其被配置为使用三字节寻址方案寻址存储器组之一,并将数据写入或从所寻址的存储体读取数据,以及耦合到 所述串行处理组件,所述指针组件包括与相应存储体相关联的两个或多个存储体寄存器指针,并且被配置为基于所述两个或多个存储体寄存器指针来选择所述存储器组之一,其中所述存储体寄存器指针组件选择 两个或多个存储器组,并且串行处理组件根据三字节寻址方案将数据写入或从所选择的存储器组中读取数据。
    • 7. 发明申请
    • SPI AUTO-BOOT MODE
    • SPI自动启动模式
    • US20090138694A1
    • 2009-05-28
    • US11945316
    • 2007-11-27
    • Anthony LeJackson Huang
    • Anthony LeJackson Huang
    • G06F15/177
    • G06F9/4403
    • Systems and methods of detecting an auto-boot mode and booting data from a serial peripheral interface to a processor without the need of a read instruction utilizing a serial peripheral interface having an auto-boot mode detector are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to serially communicate data between the processor and at least two peripherals, and an auto-boot component operably coupled to the serial processing component, comprising an auto-boot mode detector configured to determine whether a boot mode exists based on detecting whether serial input data is received during a predetermined wait state, and configured to selectively boot data to a start address associated with the processor based on the boot mode determination.
    • 提供了检测自动启动模式并将数据从串行外设接口引导到处理器的系统和方法,而不需要利用具有自动启动模式检测器的串行外围接口的读取指令。 在一个实施例中,串行外围设备接口包括被配置为在处理器和至少两个外围设备之间串行传送数据的串行处理组件,以及可操作地耦合到串行处理组件的自动启动组件,包括自动启动模式检测器, 基于检测在预定等待状态期间是否接收到串行输入数据,确定是否存在引导模式,并且被配置为基于引导模式确定来选择性地将数据引导到与处理器相关联的起始地址。
    • 8. 发明授权
    • Providing precise timing control between multiple standardized test instrumentation chassis
    • 在多个标准化测试仪器底盘之间提供精确的时序控制
    • US07366939B2
    • 2008-04-29
    • US11196873
    • 2005-08-03
    • Anthony LeGlen Gomes
    • Anthony LeGlen Gomes
    • G06F1/12
    • G01R31/31715G01R31/31716G01R31/31717G01R31/31726
    • Precise timing control across multiple standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL within each chassis, and by providing these control signals to other chassis. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system to start at the same time. A MATCH line enables pincard modules to check for expected DUT outputs and either continue execution of their local test programs or loop back and repeat a section of the local test program in accordance with the result of the DUT output check. An End Of Test (EOT) line enables any one pincard module to abruptly end the local test programs running in all other pincard modules if an error is detected by the local test program in the pincard module.
    • 通过在每个机箱内的PXI_LOCAL上提供多个控制信号,并通过向其他机箱提供这些控制信号,可以获得多个标准化机箱(如PXI)的精确时序控制。 最低共通信号(LCM)信号使所有时钟在每个LCM边沿都具有一致的时钟边沿。 启动顺序允许测试系统中的所有PXI扩展卡同时启动。 一个MATCH线使PIN卡模块能够检查预期的DUT输出,并继续执行本地测试程序或回送并根据DUT输出检查的结果重复本地测试程序的一部分。 如果pincard模块中的本地测试程序检测到错误,则测试结束(EOT)线可以使任何一个pincard模块突然结束在所有其他pincard模块中运行的本地测试程序。
    • 10. 发明授权
    • Test head Hifix for semiconductor device testing apparatus
    • 测试头Hifix用于半导体器件测试仪器
    • US06710590B1
    • 2004-03-23
    • US10319110
    • 2002-12-12
    • Niels MarkertAnthony LeHiroki YamotoRobert Sauer
    • Niels MarkertAnthony LeHiroki YamotoRobert Sauer
    • G01R3102
    • G01R31/2851
    • The present invention is directed to a test head Hifix of a semiconductor device testing apparatus that does not require disassembly for maintenance or repair of the semiconductor device testing apparatus. In one embodiment, the test head Hifix of a semiconductor device testing apparatus includes a plate that resides as the top surface of a test head and on which the assembly, loadboard, socket and DUT are mounted. The plate is attached to the test head in an arrangement that allows the plate along with the assembly, loadboard, socket and DUT to be easily moved without completely disassembling the plate, assembly and loadboard from the test head. In one embodiment, the plate is attached or coupled to the test head by hinges.
    • 本发明涉及半导体器件测试装置的测试头Hifix,其不需要拆卸用于半导体器件测试装置的维护或修理。 在一个实施例中,半导体器件测试装置的测试头Hifix包括作为测试头的顶表面的板,并且其上安装有组件,装载板,插座和DUT。 该板以允许板与组件,装载板,插座和DUT一起容易移动的布置附接到测试头,而不会完全拆卸测试头的板,组件和装载板。 在一个实施例中,板通过铰链连接或连接到测试头。