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1. 发明授权

US5852314A Thin epitaxy resurf integrated circuit containing high voltage p-channel and n-channel devices with source or drain not tied to ground 失效
标题翻译：薄的外延复原集成电路，包含高压p沟道和n沟道器件，源极或漏极不接地
公开(公告)号：US5852314A
公开(公告)日：1998-12-22
申请号：US643152
申请日：1996-04-30
申请人： Riccardo Depetro , Claudio Contiero , Antonio Andreini
发明人： Riccardo Depetro , Claudio Contiero , Antonio Andreini
IPC分类号： H01L21/8238 , H01L27/06 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/76 , H01L23/58 , H01L29/94
CPC分类号： H01L29/0878 , H01L27/0623 , H01L27/0922 , H01L29/1083 , H01L29/7816 , H01L29/7835 , H01L29/0615 , H01L29/0619 , H01L29/42368
摘要： N-channel LDMOS and p-channel MOS devices for high voltage integrated in a BiCMOS integrated circuit and exploiting a RESURF condition are provided with a buried region of the same type of conductivity of the epitaxial layer and a doping level intermediate between the doping level of the epitaxial layer and the doping level of a well region. The devices may be configured as source or drain followers without problems.
摘要翻译：集成在BiCMOS集成电路中并利用RESURF条件的用于高电压的N沟道LDMOS和p沟道MOS器件具有与外延层相同类型的导电性的掩埋区域和掺杂水平之间的掺杂水平外延层和阱区的掺杂水平。这些器件可能被配置为源或漏源从器件而没有问题。

2. 发明授权

US5777366A Integrated device with a structure for protection against high electric fields 失效
标题翻译：具有防高电场结构的集成器件
公开(公告)号：US5777366A
公开(公告)日：1998-07-07
申请号：US553154
申请日：1995-11-07
申请人： Claudio Contiero , Riccardo Depetro
发明人： Claudio Contiero , Riccardo Depetro
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/78 , H01L23/62
CPC分类号： H01L29/7816 , H01L29/7801 , H01L29/402 , H01L29/404 , H01L29/41725 , H01L29/41775 , H01L29/4238
摘要： An integrated device including a structure for protection against electric fields. The protection structure may include a first region of conducting material electrically connected to the gate/source region of the device at a first potential. The protection structure may also include a second region of conducting material electrically connected to the drain region of the device at a second potential differing from the first. In one embodiment, the first region of conducting material is comb-shaped, and includes a first number of fingers separated by a plurality of gaps. The second region of conducting material includes portions extending at the aforementioned gaps to form a comb structure. Thus, the body of semiconductor material of the device sees a protection region formed by a pair of interlocking comb structures at an intermediate potential between the first and second potentials.
摘要翻译：一种包括用于防止电场的结构的集成装置。保护结构可以包括在第一电位下电连接到器件的栅极/源极区的导电材料的第一区域。保护结构还可以包括导电材料的第二区域，该第二区域以与第一电极不同的第二电位电连接到器件的漏极区域。在一个实施例中，导电材料的第一区域是梳形的，并且包括由多个间隙分开的第一数量的手指。导电材料的第二区域包括在上述间隙处延伸以形成梳状结构的部分。因此，器件的半导体材料的主体看到由在第一和第二电位之间的中间电位的一对互锁梳结构形成的保护区域。

3. 发明授权

US08035423B2 Driving configuration of a switch 有权
标题翻译：开关配置
公开(公告)号：US08035423B2
公开(公告)日：2011-10-11
申请号：US12347517
申请日：2008-12-31
申请人： Giulio Ricotti , Riccardo Depetro
发明人： Giulio Ricotti , Riccardo Depetro
IPC分类号： H03K3/00 , H01L27/06
CPC分类号： G01S7/523 , H03K3/356113 , H03K17/04206 , H03K17/6874 , H03K2217/0054
摘要： A circuit includes a switch, having first and second transistors, and a driving device for driving the switch. A latch circuit, coupled between respective common gate and source terminals of the first and second transistors, supplies the common gate terminal with first and second control signals to turn off and on the first and second transistors. The latch circuit comprises a flip-flop coupled to the common source terminal and having a reset terminal coupled to the common source terminal by a reset resistance, a set terminal coupled to the common source terminal by a set resistance and an output terminal coupled to the common gate terminal. The latch circuit further includes an activation circuit connected to the set and reset terminals of the flip-flop and to the common source terminal to dynamically short-circuit the set and reset resistances during the falling edges of the signal applied to the switch.
摘要翻译：电路包括具有第一和第二晶体管的开关和用于驱动开关的驱动装置。耦合在第一和第二晶体管的相应公共栅极和源极端子之间的锁存电路向共用栅极端子提供第一和第二控制信号以关断第一和第二晶体管。锁存电路包括耦合到公共源极端子的触发器，并具有通过复位电阻耦合到公共源极端子的复位端子，通过设定电阻耦合到公共源极端子的设置端子和耦合到公共源极端子的输出端子普通门终端。锁存电路还包括连接到触发器的设置和复位端以及公共源极的激活电路，以在施加到开关的信号的下降沿期间动态地使设定和复位电阻短路。

4. 发明授权

US6043532A DMOS transistor protected against "snap-back" 失效
标题翻译： DMOS晶体管保护不受“快照”
公开(公告)号：US6043532A
公开(公告)日：2000-03-28
申请号：US965840
申请日：1997-11-07
申请人： Riccardo Depetro , Michele Palmieri
发明人： Riccardo Depetro , Michele Palmieri
IPC分类号： H01L29/06 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/1095 , H01L29/7802 , H01L29/4238
摘要： The DMOS transistor includes an n drain region, a p body region which forms, with the drain region, a junction having at least one edge portion with a small radius of curvature, an n+ source region which delimits a channel in the body region, p+ body contact regions, a gate electrode, a source and body electrode, and a drain electrode. To prevent the "snap-back" phenomenon when the junction is reverse biased with the source, body and gate electrodes short-circuited, a p+ region is associated with each of the edge portions having a small radius of curvature and is arranged so as to be closer to the associated edge portion than any part of the source region.
摘要翻译： DMOS晶体管包括n个漏极区域，其与漏极区域形成具有至少一个具有小曲率半径的边缘部分的接合部的p体区域，限定身体区域中的通道的n +源极区域，p +体接触区域，栅极电极，源极和主体电极以及漏极电极。为了防止当源极，主体和栅极短路时结在反向偏置时的“回扣”现象，p +区与每个具有小曲率半径的边缘部分相关联，并且布置成比源区域的任何部分更靠近相关联的边缘部分。

5. 发明授权

US09041121B2 Integrated voltage divider 有权
标题翻译：集成分压器
公开(公告)号：US09041121B2
公开(公告)日：2015-05-26
申请号：US13615220
申请日：2012-09-13
申请人： Riccardo Depetro , Aldo Vittorio Novelli , Ignazio Salvatore Bellomo
发明人： Riccardo Depetro , Aldo Vittorio Novelli , Ignazio Salvatore Bellomo
IPC分类号： H01L27/06 , H01K1/18 , H01L29/78 , H01L29/861 , H01L49/02 , H01L29/06
CPC分类号： H01L29/7817 , H01L28/20 , H01L29/0692 , H01L29/0696 , H01L29/7818 , H01L29/861
摘要： A semiconductor structure including a high-voltage transistor; voltage dropping circuitry, at least part of which is overlapping the high-voltage transistor; at least one intermediate contact point to the voltage dropping circuitry, connected to at least one intermediate position between a first and a second end of the voltage dropping circuitry; and at least one external connection connecting the at least one intermediate contact point to outside of the semiconductor structure.
摘要翻译：一种包括高压晶体管的半导体结构; 降压电路，其至少一部分与高压晶体管重叠; 至少一个到所述降压电路的中间接触点，连接到所述降压电路的第一和第二端之间的至少一个中间位置; 以及将所述至少一个中间接触点连接到所述半导体结构外部的至少一个外部连接。

6. 发明申请

US20100075484A1 SOI DEVICE WITH CONTACT TRENCHES FORMED DURING EPITAXIAL GROWING 有权
标题翻译：在外延生长期间形成接触层的SOI器件
公开(公告)号：US20100075484A1
公开(公告)日：2010-03-25
申请号：US12610463
申请日：2009-11-02
申请人： Pietro Montanini , Giuseppe Ammendola , Riccardo Depetro , Marta Mottura
发明人： Pietro Montanini , Giuseppe Ammendola , Riccardo Depetro , Marta Mottura
IPC分类号： H01L21/762
CPC分类号： H01L21/84 , H01L21/26586 , H01L21/3226 , H01L21/76264 , H01L27/1207
摘要： A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.
摘要翻译：一种集成电子装置的制造方法。该方法包括提供具有半导体衬底的SOI衬底，半导体衬底上的绝缘层和绝缘层上的半导体起始层; 外延生长所述起始层以在所述绝缘层上获得用于积分所述器件的部件的半导体有源层，以及在所述起始层的外延生长步骤之前形成从所述起始层的暴露表面延伸到所述半导体衬底的至少一个接触沟槽层，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的相应部分，外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。

7. 发明申请

US20070296036A1 SOI device with contact trenches formed during epitaxial growing 有权
标题翻译：在外延生长期间形成接触沟槽的SOI器件
公开(公告)号：US20070296036A1
公开(公告)日：2007-12-27
申请号：US11820393
申请日：2007-06-19
申请人： Pietro Montanini , Giuseppe Ammendola , Riccardo Depetro , Marta Mottura
发明人： Pietro Montanini , Giuseppe Ammendola , Riccardo Depetro , Marta Mottura
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L21/26586 , H01L21/3226 , H01L21/76264 , H01L27/1207
摘要： A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.
摘要翻译：一种集成电子装置的制造方法。该方法包括提供具有半导体衬底的SOI衬底，半导体衬底上的绝缘层和绝缘层上的半导体起始层; 外延生长所述起始层以在所述绝缘层上获得用于积分所述器件的部件的半导体有源层，以及在所述起始层的外延生长步骤之前形成从所述起始层的暴露表面延伸到所述半导体衬底的至少一个接触沟槽层，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的相应部分，外延生长被进一步施加到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。

8. 发明申请

US20070141809A1 Process for the singulation of integrated devices in thin semiconductor chips 有权
标题翻译：半导体芯片中集成器件的单片化处理
公开(公告)号：US20070141809A1
公开(公告)日：2007-06-21
申请号：US11584259
申请日：2006-10-19
申请人： Anna Ponza , Riccardo Depetro , Pietro Montanini
发明人： Anna Ponza , Riccardo Depetro , Pietro Montanini
IPC分类号： H01L21/00
CPC分类号： H01L21/78
摘要： A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer partially suspended above a semiconductor substrate and constrained to the substrate by temporary anchorages; dividing the layer into a plurality of portions laterally separated from one another; and removing the temporary anchorages, in order to free the portions.
摘要翻译：用于制造半导体芯片中的集成器件的方法设想：形成半导体层，部分地悬置在半导体衬底之上，并通过临时锚固被约束到衬底; 将层分成彼此横向分离的多个部分; 并移除临时锚地，以释放这些部分。

9. 发明授权

US06194948B1 Method and an auxiliary circuit for preventing the triggering of a parasitic transistor in an output stage of an electronic circuit 失效
标题翻译：用于防止在电子电路的输出级中触发寄生晶体管的方法和辅助电路
公开(公告)号：US06194948B1
公开(公告)日：2001-02-27
申请号：US09106583
申请日：1998-06-29
申请人： Enrico Scian , Fabrizio Martignoni , Riccardo Depetro
发明人： Enrico Scian , Fabrizio Martignoni , Riccardo Depetro
IPC分类号： H03K1730
CPC分类号： H03K19/00315 , G05F3/205 , H01L27/0251
摘要： A method, and related circuit, prevent the triggering of a parasitic transistor in an output stage of an electronic circuit. The stage includes a transistor pair with at least one transistor of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor having a terminal connected to the body terminal. The method includes the steps of providing a capacitor connected between the body and source terminals of the PMOS transistor; and using a control circuit to suppress the body effect of the pull-up PMOS transistor.
摘要翻译：一种方法和相关电路防止在电子电路的输出级中触发寄生晶体管。该级包括具有至少一个上拉PMOS型晶体管的晶体管对，其具有相应的源极，栅极和漏极端子以及主体端子，以及具有连接到主体端子的端子的寄生双极晶体管。该方法包括以下步骤：提供连接在PMOS晶体管的主体和源极端子之间的电容器; 并且使用控制电路来抑制上拉PMOS晶体管的体效应。

10. 发明授权

US07572703B2 Method for manufacturing a vertical-gate MOS transistor with countersunk trench-gate 有权
标题翻译：制造具有埋头沟槽栅极的垂直栅极MOS晶体管的方法
公开(公告)号：US07572703B2
公开(公告)日：2009-08-11
申请号：US11558283
申请日：2006-11-09
申请人： Marco Annese , Pietro Montanini , Riccardo Depetro
发明人： Marco Annese , Pietro Montanini , Riccardo Depetro
IPC分类号： H01L21/336
CPC分类号： H01L29/1037 , H01L29/4236 , H01L29/42376 , H01L29/66621 , H01L29/78
摘要： A method manufactures a vertical-gate MOS transistor integrated in a semiconductor chip having a main surface. The method includes: forming a trench gate extending into the chip from the main surface to a gate depth, by forming a control gate and an insulation layer for insulating the control gate from the chip. Forming the trench gate includes: forming a trench extending into the chip from the main surface to a protection depth less than the gate depth, the trench having a lateral wall and a bottom wall with an edge portion of the lateral wall extending from the main surface being inclined outwardly with respect to the remaining portion of the lateral wall; forming a first auxiliary insulation layer in the trench; removing a bottom wall of the first auxiliary insulation layer; extending the trench to the gate depth; and forming a second auxiliary insulation layer in the trench.
摘要翻译：一种制造集成在具有主表面的半导体芯片中的垂直栅极MOS晶体管的方法。该方法包括：通过形成用于使控制栅极与芯片绝缘的控制栅极和绝缘层，形成从主表面延伸到栅极深度的沟槽栅极。形成沟槽栅包括：形成从主表面延伸到芯片的沟槽到小于栅极深度的保护深度，沟槽具有侧壁和底壁，侧壁的边缘部分从主表面延伸相对于侧壁的剩余部分向外倾斜; 在沟槽中形成第一辅助绝缘层; 移除所述第一辅助绝缘层的底壁; 将沟槽延伸到浇口深度; 以及在沟槽中形成第二辅助绝缘层。

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