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1. 发明申请

US20070141787A1 METHOD FOR MANUFACTURING A VERTICAL-GATE MOS TRANSISTOR WITH COUNTERSUNK TRENCH-GATE 有权
标题翻译：具有反激式TRENCH-GATE的垂直栅MOS晶体管的制造方法
公开(公告)号：US20070141787A1
公开(公告)日：2007-06-21
申请号：US11558283
申请日：2006-11-09
申请人： Marco Annese , Pietro Montanini , Riccardo Depetro
发明人： Marco Annese , Pietro Montanini , Riccardo Depetro
IPC分类号： H01L21/336
CPC分类号： H01L29/1037 , H01L29/4236 , H01L29/42376 , H01L29/66621 , H01L29/78
摘要： A method manufactures a vertical-gate MOS transistor integrated in a semiconductor chip having a main surface. The method includes: forming a trench gate extending into the chip from the main surface to a gate depth, by forming a control gate and an insulation layer for insulating the control gate from the chip. Forming the trench gate includes: forming a trench extending into the chip from the main surface to a protection depth less than the gate depth, the trench having a lateral wall and a bottom wall with an edge portion of the lateral wall extending from the main surface being inclined outwardly with respect to the remaining portion of the lateral wall; forming a first auxiliary insulation layer in the trench; removing a bottom wall of the first auxiliary insulation layer; extending the trench to the gate depth; and forming a second auxiliary insulation layer in the trench.
摘要翻译：一种制造集成在具有主表面的半导体芯片中的垂直栅极MOS晶体管的方法。该方法包括：通过形成用于使控制栅极与芯片绝缘的控制栅极和绝缘层，形成从主表面延伸到栅极深度的沟槽栅极。形成沟槽栅包括：形成从主表面延伸到芯片的沟槽到小于栅极深度的保护深度，沟槽具有侧壁和底壁，侧壁的边缘部分从主表面延伸相对于侧壁的剩余部分向外倾斜; 在沟槽中形成第一辅助绝缘层; 移除所述第一辅助绝缘层的底壁; 将沟槽延伸到浇口深度; 以及在沟槽中形成第二辅助绝缘层。

2. 发明授权

US07572703B2 Method for manufacturing a vertical-gate MOS transistor with countersunk trench-gate 有权
标题翻译：制造具有埋头沟槽栅极的垂直栅极MOS晶体管的方法
公开(公告)号：US07572703B2
公开(公告)日：2009-08-11
申请号：US11558283
申请日：2006-11-09
申请人： Marco Annese , Pietro Montanini , Riccardo Depetro
发明人： Marco Annese , Pietro Montanini , Riccardo Depetro
IPC分类号： H01L21/336
CPC分类号： H01L29/1037 , H01L29/4236 , H01L29/42376 , H01L29/66621 , H01L29/78
摘要： A method manufactures a vertical-gate MOS transistor integrated in a semiconductor chip having a main surface. The method includes: forming a trench gate extending into the chip from the main surface to a gate depth, by forming a control gate and an insulation layer for insulating the control gate from the chip. Forming the trench gate includes: forming a trench extending into the chip from the main surface to a protection depth less than the gate depth, the trench having a lateral wall and a bottom wall with an edge portion of the lateral wall extending from the main surface being inclined outwardly with respect to the remaining portion of the lateral wall; forming a first auxiliary insulation layer in the trench; removing a bottom wall of the first auxiliary insulation layer; extending the trench to the gate depth; and forming a second auxiliary insulation layer in the trench.
摘要翻译：一种制造集成在具有主表面的半导体芯片中的垂直栅极MOS晶体管的方法。该方法包括：通过形成用于使控制栅极与芯片绝缘的控制栅极和绝缘层，形成从主表面延伸到栅极深度的沟槽栅极。形成沟槽栅包括：形成从主表面延伸到芯片的沟槽到小于栅极深度的保护深度，沟槽具有侧壁和底壁，侧壁的边缘部分从主表面延伸相对于侧壁的剩余部分向外倾斜; 在沟槽中形成第一辅助绝缘层; 移除所述第一辅助绝缘层的底壁; 将沟槽延伸到浇口深度; 以及在沟槽中形成第二辅助绝缘层。

3. 发明申请

US20070034895A1 Folded-gate MOS transistor 有权
标题翻译：折叠栅MOS晶体管
公开(公告)号：US20070034895A1
公开(公告)日：2007-02-15
申请号：US11482531
申请日：2006-07-06
申请人： Pietro Montanini , Marco Annese , Lucia Zullino
发明人： Pietro Montanini , Marco Annese , Lucia Zullino
IPC分类号： H01L29/74
CPC分类号： H01L29/66621 , H01L21/2652 , H01L29/0684 , H01L29/0847 , H01L29/6659 , H01L29/7834
摘要： An insulated-gate transistor includes a semiconductor layer of a first conductivity type, an insulated gate comprising a trench gate extending into the semiconductor layer, a source and a drain regions of a second conductivity type formed in the semiconductor layer at respective sides of the trench gate, wherein each one of the source and drain regions includes a first doped region, having a first dopant concentration, formed in the semiconductor layer adjacent to the trench gate, said first dopant concentration being such that a breakdown voltage of the junction formed by the first doped region and the semiconductor layer is higher than a predetermined breakdown voltage, and a second doped region, having a second dopant concentration higher than the first dopant concentration, said second doped region being formed in the first doped region and being spaced apart from the trench gate, the second dopant concentration being adapted to form a non-rectifying contact for electrically contacting the first doped region.
摘要翻译：绝缘栅晶体管包括第一导电类型的半导体层，包括延伸到半导体层中的沟槽栅极的绝缘栅极，在沟槽的相应侧上形成在半导体层中的第二导电类型的源极和漏极区域栅极，其中源极和漏极区域中的每一个包括形成在与沟槽栅极相邻的半导体层中的第一掺杂剂浓度的第一掺杂区域，所述第一掺杂剂浓度使得由所述栅极形成的结的击穿电压第一掺杂区和半导体层高于预定的击穿电压，第二掺杂区具有比第一掺杂浓度高的第二掺杂浓度，所述第二掺杂区形成在第一掺杂区中并与第一掺杂区间隔开沟槽栅极，第二掺杂剂浓度适于形成用于电连接的非整流接触第一个掺杂区域。

4. 发明授权

US07629645B2 Folded-gate MOS transistor 有权
标题翻译：折叠栅MOS晶体管
公开(公告)号：US07629645B2
公开(公告)日：2009-12-08
申请号：US11482531
申请日：2006-07-06
申请人： Pietro Montanini , Marco Annese , Lucia Zullino
发明人： Pietro Montanini , Marco Annese , Lucia Zullino
IPC分类号： H01L29/78
CPC分类号： H01L29/66621 , H01L21/2652 , H01L29/0684 , H01L29/0847 , H01L29/6659 , H01L29/7834
摘要： An insulated-gate transistor includes a semiconductor layer of a first conductivity type, an insulated gate comprising a trench gate extending into the semiconductor layer, a source and a drain regions of a second conductivity type formed in the semiconductor layer at respective sides of the trench gate, wherein each one of the source and drain regions includes a first doped region, having a first dopant concentration, formed in the semiconductor layer adjacent to the trench gate, said first dopant concentration being such that a breakdown voltage of the junction formed by the first doped region and the semiconductor layer is higher than a predetermined breakdown voltage, and a second doped region, having a second dopant concentration higher than the first dopant concentration, said second doped region being formed in the first doped region and being spaced apart from the trench gate, the second dopant concentration being adapted to form a non-rectifying contact for electrically contacting the first doped region.
摘要翻译：绝缘栅晶体管包括第一导电类型的半导体层，包括延伸到半导体层中的沟槽栅极的绝缘栅极，在沟槽的相应侧上形成在半导体层中的第二导电类型的源极和漏极区域栅极，其中源极和漏极区域中的每一个包括形成在与沟槽栅极相邻的半导体层中的第一掺杂剂浓度的第一掺杂区域，所述第一掺杂剂浓度使得由所述栅极形成的结的击穿电压第一掺杂区和半导体层高于预定的击穿电压，第二掺杂区具有比第一掺杂浓度高的第二掺杂浓度，所述第二掺杂区形成在第一掺杂区中并与第一掺杂区间隔开沟槽栅极，第二掺杂剂浓度适于形成用于电连接的非整流接触第一个掺杂区域。

5. 发明申请

US20070145474A1 VERTICAL-GATE MOS TRANSISTOR FOR HIGH VOLTAGE APPLICATIONS WITH DIFFERENTIATED OXIDE THICKNESS 审中-公开
标题翻译：用于具有差异氧化物厚度的高压应用的垂直栅MOS晶体管
公开(公告)号：US20070145474A1
公开(公告)日：2007-06-28
申请号：US11558285
申请日：2006-11-09
申请人： Marco Annese , Fabrizio Toia , Pietro Montanini
发明人： Marco Annese , Fabrizio Toia , Pietro Montanini
IPC分类号： H01L31/00
CPC分类号： H01L21/28167 , H01L29/42368 , H01L29/66621 , H01L29/7834
摘要： A vertical-gate MOS transistor is integrated in a semiconductor chip of a first conductivity type having a main surface, and includes an insulated trench gate extending into the semiconductor chip from the main surface to a gate depth. The trench gate includes a control gate and an insulation layer for insulating the control gate from the semiconductor chip, source and drain regions of a second conductivity type formed in the semiconductor chip, at least one of the source and drain regions being adjacent to the insulation layer and extending into the semiconductor chip from the main surface to a region depth lower than the gate depth. The insulation layer includes an outer portion, extending into the semiconductor chip to a protection depth less than the gate depth, and an inner portion, the outer portion having first thickness and the internal portion having a second thickness less than the first thickness.
摘要翻译：垂直栅极MOS晶体管集成在具有主表面的第一导电类型的半导体芯片中，并且包括从主表面延伸到栅极深度的半导体芯片中的绝缘沟槽栅极。沟槽栅极包括控制栅极和绝缘层，用于将控制栅极与形成在半导体芯片中的第二导电类型的半导体芯片，源极和漏极区域绝缘，源极和漏极区域中的至少一个与绝缘体相邻并且从主表面延伸到半导体芯片到比栅深度低的区域。绝缘层包括延伸到半导体芯片中的保护深度小于栅极深度的外部部分，以及内部部分，外部部分具有第一厚度，而内部部分具有小于第一厚度的第二厚度。

6. 发明申请

US20130049171A1 METHOD FOR PRODUCING SEMICONDUCTOR COMPONENTS ON A SUBSTRATE, AND SUBSTRATE COMPRISING SEMICONDUCTOR COMPONENTS 有权
标题翻译：在基板上生产半导体元件的方法和包含半导体元件的基板
公开(公告)号：US20130049171A1
公开(公告)日：2013-02-28
申请号：US13593933
申请日：2012-08-24
申请人： Martin POPP , Beat De Coi , Marco Annese
发明人： Martin POPP , Beat De Coi , Marco Annese
IPC分类号： G03F7/20 , H01L29/06
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338
摘要： A method for producing semiconductor components on a substrate including photolithographic patterning steps, in which method, on the substrate, a first layer to be patterned is applied and a second layer serving as a mask layer for the first layer to be patterned is applied, wherein a third layer serving as a mask for the second layer is applied, and wherein at least two photolithographic patterning processes are carried out successively for the second layer, wherein, during one of the patterning processes, after the production of a structure made from a photosensitive layer for the provision of a mask layer for a patterning process at the third layer, positive ramp angles α are produced at the patterning edges of the third layer, as a result of which the structures remaining free, given a thickness h of the third layer, decrease in size by a value D=2*h/tan α.
摘要翻译：一种用于在包括光刻图案步骤的基板上制造半导体部件的方法，其中施加了在基板上形成要构图的第一层的方法，并且施加用作待图案化第一层的掩模层的第二层，其中施加用作第二层的掩模的第三层，并且其中对于第二层连续执行至少两个光刻图案化工艺，其中在一个图案化工艺期间，在制造由感光材料制成的结构之后层，用于在第三层提供用于图案化工艺的掩模层，在第三层的图案化边缘处产生正斜面角α，结果，给定第三层的厚度h，结构保持游离，尺寸减小值D = 2 * h /tanα。

7. 发明授权

US08901690B2 Semiconductor structure for photon detection 有权
标题翻译：用于光子检测的半导体结构
公开(公告)号：US08901690B2
公开(公告)日：2014-12-02
申请号：US13551732
申请日：2012-07-18
申请人： Martin Popp , Beat De Coi , Marco Annese
发明人： Martin Popp , Beat De Coi , Marco Annese
IPC分类号： H01L27/146 , H01L27/148 , H01L31/18 , H01L31/0216 , H01L31/0232 , H01L31/101
CPC分类号： H01L27/1463
摘要： A semiconductor structure for photon detection, comprising a substrate composed of a semiconductor material having a first doping, a contact region fitted at the frontside of the substrate, a bias layer composed of a semiconductor material having a second doping, which is arranged on the backside of the substrate at a distance from the contact region, wherein the contact region at least partly lies opposite the bias layer, such that an overlap region is present in a lateral direction, a guard ring, which is arranged at the frontside of the substrate and surrounds the contact region, wherein a reverse voltage can be applied between the contact region and the guard ring. In order to enable more cost-effective production, the overlap region has a lateral extent amounting to at least one quarter of the distance between contact region and bias layer.
摘要翻译：一种用于光子检测的半导体结构，包括由具有第一掺杂的半导体材料构成的衬底，安装在衬底的前侧的接触区域，由具有第二掺杂的半导体材料组成的偏置层，其布置在背面所述接触区域至少部分地与所述偏置层相对，使得重叠区域在横向方向上存在，保护环布置在所述基板的前侧，并且所述保护环设置在所述基板的前侧;以及围绕接触区域，其中可以在接触区域和保护环之间施加反向电压。为了实现更具成本效益的生产，重叠区域具有等于接触区域和偏置层之间的距离的至少四分之一的横向范围。

8. 发明授权

US08802566B2 Method for producing semiconductor components on a substrate, and substrate comprising semiconductor components 有权
标题翻译：在基板上制造半导体部件的方法以及包括半导体部件的基板
公开(公告)号：US08802566B2
公开(公告)日：2014-08-12
申请号：US13593933
申请日：2012-08-24
申请人： Martin Popp , Beat De Coi , Marco Annese
发明人： Martin Popp , Beat De Coi , Marco Annese
IPC分类号： G03F7/20 , H01L29/96 , H01L21/3213 , H01L21/033
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338
摘要： A method for producing semiconductor components on a substrate including photolithographic patterning steps, in which method, on the substrate, a first layer to be patterned is applied and a second layer serving as a mask layer for the first layer to be patterned is applied, wherein a third layer serving as a mask for the second layer is applied, and wherein at least two photolithographic patterning processes are carried out successively for the second layer, wherein, during one of the patterning processes, after the production of a structure made from a photosensitive layer for the provision of a mask layer for a patterning process at the third layer, positive ramp angles α are produced at the patterning edges of the third layer, as a result of which the structures remaining free, given a thickness h of the third layer, decrease in size by a value D=2*h/tan α.
摘要翻译：一种用于在包括光刻图案步骤的基板上制造半导体部件的方法，其中施加了在基板上形成要构图的第一层的方法，并且施加用作待图案化第一层的掩模层的第二层，其中施加用作第二层的掩模的第三层，并且其中对于第二层连续执行至少两个光刻图案化工艺，其中在一个图案化工艺期间，在制造由感光材料制成的结构之后层，用于在第三层提供用于图案化工艺的掩模层，在第三层的图案化边缘处产生正斜面角α，结果，给定第三层的厚度h，结构保持游离，尺寸减小值D = 2 * h /tanα。

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