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1. 发明授权

US06426904B2 Structures for wafer level test and burn-in 失效
标题翻译：晶圆级测试和老化的结构
公开(公告)号：US06426904B2
公开(公告)日：2002-07-30
申请号：US09803500
申请日：2001-03-09
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译：晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低了老化所需的时间。沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

2. 发明授权

US5563086A Integrated memory cube, structure and fabrication 失效
标题翻译：集成存储立方体，结构和制造
公开(公告)号：US5563086A
公开(公告)日：1996-10-08
申请号：US406284
申请日：1995-03-17
申请人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
发明人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
IPC分类号： G11C5/00 , H01L25/065 , H01L21/70
CPC分类号： H01L25/0657 , G11C5/06 , H01L2224/48091 , H01L2225/0651 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/10253
摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译：一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

3. 发明授权

US5571754A Method of fabrication of endcap chip with conductive, monolithic L-connect for multichip stack 失效
标题翻译：用于多芯片堆叠的具有导电的单片L形连接器的端盖芯片的制造方法
公开(公告)号：US5571754A
公开(公告)日：1996-11-05
申请号：US555738
申请日：1995-11-09
申请人： Claude L. Bertin , Wayne J. Howell , Howard L. Kalter
发明人： Claude L. Bertin , Wayne J. Howell , Howard L. Kalter
IPC分类号： H01L23/538 , H01L25/065 , H01L25/07 , H01L25/18 , H01L21/60
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/24145 , H01L2224/32145 , H01L2224/48145 , H01L2225/06506 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06586 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/19041
摘要： An endcap chip is provided for a multichip stack comprising multiple integrated circuit chips laminated together. The endcap chip has a substrate with an upper surface and a edge surface, which extends in a plane orthogonal to the upper surface. At least one conductive, monolithic L-connect is disposed over the substrate such that a first leg extends at least partially over the upper surface of the substrate and a second leg extends at least partially over the edge surface of the substrate. When the endcap chip is located at the end of the multichip stack, the at least one conductive, monolithic L-connect electrically connects metal on an end face of the stack to metal on a side face of the stack. A fabrication process is set forth for producing the endcap chip with lithographically defined dimensions.
摘要翻译：提供了一种用于多芯片堆叠的端盖芯片，其包括层叠在一起的多个集成电路芯片。端盖芯片具有上表面和边缘表面的基板，该基板在与上表面正交的平面中延伸。至少一个导电的单片L形连接器设置在衬底上，使得第一腿部至少部分地延伸到衬底的上表面上，并且第二腿部至少部分地延伸到衬底的边缘表面上。当端盖芯片位于多芯片堆叠的端部时，至少一个导电的单片L形连接器将堆叠的端面上的金属与堆叠的侧面上的金属电连接。阐述了用于制造具有光刻尺寸的端盖芯片的制造工艺。

4. 发明授权

US5561622A Integrated memory cube structure 失效
标题翻译：集成内存立方体结构
公开(公告)号：US5561622A
公开(公告)日：1996-10-01
申请号：US120993
申请日：1993-09-13
申请人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
发明人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , Gordon A. Kelley, Jr.
IPC分类号： G11C5/00 , H01L25/065 , G11C5/06 , H01L23/02
CPC分类号： H01L25/0657 , G11C5/06 , H01L2224/48091 , H01L2225/0651 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/10253
摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译：一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

5. 发明授权

US06233184B1 Structures for wafer level test and burn-in 失效
标题翻译：晶圆级测试和老化的结构
公开(公告)号：US06233184B1
公开(公告)日：2001-05-15
申请号：US09191954
申请日：1998-11-13
申请人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
发明人： John E. Barth , Claude L. Bertin , Jeffrey H. Dreibelbis , Wayne F. Ellis , Wayne J. Howell , Erik L. Hedberg , Howard L. Kalter , William R. Tonti , Donald L. Wheater
IPC分类号： G11C2900
CPC分类号： G01R31/2855 , G01R31/2806 , G01R31/2831 , G01R31/31905 , H01L2224/05624 , H01L2224/13 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014
摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
摘要翻译：晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。

6. 发明授权

US5517754A Fabrication processes for monolithic electronic modules 失效
标题翻译：单片电子模块的制造工艺
公开(公告)号：US5517754A
公开(公告)日：1996-05-21
申请号：US252794
申请日：1994-06-02
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Wayne J. Howell
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Wayne J. Howell
IPC分类号： H01L21/28 , H01L21/98 , H01L25/065 , H05K3/34
CPC分类号： H01L25/50 , H01L25/0657 , H01L2224/24145 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , Y10S269/903 , Y10S269/909 , Y10S428/914 , Y10T29/49124 , Y10T29/49144 , Y10T428/14 , Y10T428/1438 , Y10T428/1481 , Y10T428/24942
摘要： This invention comprises various high production methods for simultaneously forming surface metallizations on a plurality of monolithic electronic modules. Each monolithic electronic module may comprise a single semiconductor chip or multiple semiconductor chips. The methods can employ a workpiece which automatically discontinues side surface metallization between different electronic modules in the stack. Multiple workpieces are interleaved within the stack between the electronic modules. Each workpiece may include a transfer layer(s) for permanent bonding to an end surface of an adjacent electronic module in the stack. This transfer layer may comprise an insulation layer, a metallization layer, an active circuit layer, or any combination thereof. End surface metallization can thus be provided contemporaneous with side surface metallization of multiple electronic modules.
摘要翻译：本发明包括用于在多个单片电子模块上同时形成表面金属化的各种高生产方法。每个单片电子模块可以包括单个半导体芯片或多个半导体芯片。该方法可以采用自动中断堆叠中不同电子模块之间的侧面金属化的工件。多个工件在电子模块之间的堆叠内交错。每个工件可以包括用于永久地结合到堆叠中的相邻电子模块的端面的转移层。该转移层可以包括绝缘层，金属化层，有源电路层或其任何组合。因此，可以同时提供多个电子模块的侧表面金属化的端面金属化。

7. 发明授权

US5596226A Semiconductor chip having a chip metal layer and a transfer metal and corresponding electronic module 失效
标题翻译：具有芯片金属层和由相同金属组成的转移金属层的半导体芯片及相应的电子模块
公开(公告)号：US5596226A
公开(公告)日：1997-01-21
申请号：US301290
申请日：1994-09-06
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Timothy H. Daubenspeck , Wayne J. Howell
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , Timothy H. Daubenspeck , Wayne J. Howell
IPC分类号： H01L25/18 , H01L21/02 , H01L21/301 , H01L21/3205 , H01L21/822 , H01L21/98 , H01L23/52 , H01L25/065 , H01L25/07 , H01L27/00 , H01L27/04 , H01L23/48
CPC分类号： H01L25/50 , H01L24/24 , H01L25/0657 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2924/14
摘要： A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.
摘要翻译：一种制造方法，包括半导体芯片切痕工艺以及由此形成的半导体芯片和电子模块。制造方法包括提供包括多个集成电路芯片的晶片，其中它们之间具有切口区域。芯片金属化存在于切口区域内。使用光刻工艺来保护仅暴露切口区域的晶片。接下来，蚀刻晶片，从切口区域清除芯片金属化。然后切割晶片，并且将芯片堆叠以形成单片电子模块。处理电子模块的侧表面以暴露延伸到其上的转移金属，从而便于与电子模块内的芯片的电连接。阐述了制造方法的具体细节，所得到的集成电路芯片和单片电子模块。

8. 发明授权

US5502333A Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit 失效
标题翻译：半导体堆叠结构和利用可编程备用电路的制造/备用方法
公开(公告)号：US5502333A
公开(公告)日：1996-03-26
申请号：US220086
申请日：1994-03-30
申请人： Claude L. Bertin , Erik L. Hedberg , Wayne J. Howell
发明人： Claude L. Bertin , Erik L. Hedberg , Wayne J. Howell
IPC分类号： H01L21/66 , H01L23/538 , H01L25/065 , H01L25/18 , H01L23/02
CPC分类号： H01L24/49 , G11C29/808 , H01L22/22 , H01L23/5382 , H01L25/0657 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/4911 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06582 , H01L2225/06596 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01058 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15312 , H01L2924/181 , H01L2924/19107
摘要： Electronic semiconductor structures utilize an electrically programmable spare circuit incorporated with a multichip package. The programmable sparing capability in the multichip package is accomplished either with or without the inclusion of a spare chip(s). With a spare memory circuit, individual failed memory cells in the semiconductor chips of a stack can be functionally replaced by memory cells of the spare memory circuit subsequent to encapsulation and burn-in testing. With use of a spare chip, non-volatile sparing can occur subsequent to encapsulation and burn-in testing without physical rewiring of a wire bond connection. Specific details of alternate electronic semiconductor structures, and fabrication and sparing methods therefore, are set forth.
摘要翻译：电子半导体结构利用并入多芯片封装的电可编程备用电路。多芯片封装中的可编程保护功能可以在有或没有包含备用芯片的情况下完成。利用备用存储器电路，在封装和老化测试之后，堆叠的半导体芯片中的单个故障存储器单元可以在功能上被备用存储器电路的存储单元替代。使用备用芯片，在封装和老化测试之后可能会发生非易失性保护，而无需线接合连接的物理重新布线。因此，提出了替代电子半导体结构的具体细节，以及制造和备用方法。

9. 发明授权

US5466634A Electronic modules with interconnected surface metallization layers and fabrication methods therefore 失效
标题翻译：因此，具有互连表面金属化层的电子模块和制造方法
公开(公告)号：US5466634A
公开(公告)日：1995-11-14
申请号：US359982
申请日：1994-12-20
申请人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
发明人： Kenneth E. Beilstein, Jr. , Claude L. Bertin , John E. Cronin , Wayne J. Howell , James M. Leas , Robert B. Phillips
IPC分类号： H01L23/538 , H01L21/98 , H01L25/065 , H01L25/07 , H01L25/18 , H01L21/44
CPC分类号： H01L25/50 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/24145 , H01L2224/48091 , H01L2224/49109 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06596 , H01L2924/30107
摘要： Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results. Specific details of electronic modules, IC chips contained therein, and stacks composed thereof are also set forth.
摘要翻译：阐述了具有电互连的侧表面金属化层和相关的电子模块的电子模块的制造方法。所述方法包括提供包括多个堆叠的IC芯片的堆叠。在堆叠上形成侧面薄膜金属化层。接下来，将端面薄膜金属化层形成为堆叠，使得侧表面和端面薄膜金属化层直接电互连。或者，堆叠的每个IC芯片可以包括端面金属化层，使得不需要在堆叠的端表面上分离形成端面金属化层。所述方法还包括通过首先提供长堆叠的IC芯片，测试堆叠的芯片，然后基于测试结果将长堆叠分成多个小堆功能IC芯片来形成电子模块。还阐述了电子模块，其中包含的IC芯片及其组成的具体细节。

10. 发明授权

US07132841B1 Carrier for test, burn-in, and first level packaging 失效
标题翻译：用于测试，老化和一级包装的载体
公开(公告)号：US07132841B1
公开(公告)日：2006-11-07
申请号：US09588617
申请日：2000-06-06
申请人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
发明人： Claude L. Bertin , Wayne F. Ellis , Mark W. Kellogg , William R. Tonti , Jerzy M. Zalesinski , James M. Leas , Wayne J. Howell
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/2867 , G11C5/04 , G11C29/06 , G11C29/1201 , G11C29/48 , G11C29/56016 , G11C29/785 , G11C2029/2602 , G11C2029/5602 , H01L22/22 , H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier. The carrier is formed of a flex material. It can also be formed of printed circuit board material. A window in the flex permits invoking redundancy on each chip after burn-in is complete, significantly improving yield as compared with present schemes that do not permit repair after burn-in.
摘要翻译：在载体上提供多个半导体器件用于测试或烧录。然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。载体用作每个芯片的第一级封装。因此，载体用于测试和烧录和包装的双重目的。可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。载体由柔性材料形成。它也可以由印刷电路板材料形成。柔性窗口允许在烧坏完成后在每个芯片上调用冗余度，与不允许在老化后修复的现有方案相比，显着提高产量。

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