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1. 发明授权

US5568477A Multipurpose packet switching node for a data communication network 失效
标题翻译：用于数据通信网络的多用途分组交换节点
公开(公告)号：US5568477A
公开(公告)日：1996-10-22
申请号：US495774
申请日：1995-06-27
申请人： Claude Galand , Xavier Jacquart , Gerald Lebizay , Jean-yves Leboudec , Philippe Louis , Clement Poiraud , Eric S. Georges , Victor Spagnol , Edward Suffern , Hong L. Truong
发明人： Claude Galand , Xavier Jacquart , Gerald Lebizay , Jean-yves Leboudec , Philippe Louis , Clement Poiraud , Eric S. Georges , Victor Spagnol , Edward Suffern , Hong L. Truong
IPC分类号： H04Q3/00 , H04L12/56 , H04L12/64 , H04Q11/04 , H04J3/24
CPC分类号： H04L49/3009 , H04L49/30 , H04L49/3081 , H04Q11/0478 , H04L2012/5662 , H04L2012/5668 , H04L49/20 , H04L49/25
摘要： A multipurpose data communication network node for interconnecting both ATM and Variable Length (VL) input/output trunks with all combinations of node input versus output trunk connections. The network node includes ATM/VL Receive Adapters and ATM/VL Transmit Adapters, interconnected via a Switching device (44) operating on ATM like packets (i.e. ATM cells) only. The receive adapter includes means (41, 43) for deriving switchable cells from VL traffic possibly including ATM packets and provided over an input VL trunk and means (45, 46) for deriving switchable cells from ATM packets provided on input ATM trunk. The transmit adapter, includes means (47, 48) for reconstructing VL traffic to be fed onto an output VL trunk, and means (49, 50) for reconstructing ATM traffic to be fed onto an output ATM trunk; both means (47, 48) and (49, 50) being fed with switchable cells irrespective of the traffic origin, being it from VL or ATM trunks.
摘要翻译：用于将ATM和可变长度（VL）输入/输出中继线与节点输入与输出中继线连接的所有组合相互连接的多用途数据通信网络节点。网络节点包括ATM / VL接收适配器和ATM / VL发送适配器，其通过仅在ATM上作为分组（即ATM信元）运行的交换设备（44）互连。接收适配器包括用于从可能包括ATM分组并经由输入VL中继提供的VL业务导出可切换小区的装置（41,43）以及用于从提供在输入ATM中继线上的ATM分组导出可切换小区的装置（45,46）。发射适配器包括用于重建要馈送到输出VL中继线上的VL业务的装置（47,48），以及用于重建要馈送到输出ATM中继线上的ATM业务的装置（49,50）两个装置（47,48）和（49,50）都与可交换电池一起馈送，而不管交通来源是否来自VL或ATM中继线。

2. 发明授权

US5923667A System and method for creating N-times bandwidth from N separate physical lines 失效
标题翻译：从N个独立物理线路创建N倍带宽的系统和方法
公开(公告)号：US5923667A
公开(公告)日：1999-07-13
申请号：US807496
申请日：1997-02-27
申请人： Clement Poiraud , Edward Suffern , Spiros Teleoglou
发明人： Clement Poiraud , Edward Suffern , Spiros Teleoglou
IPC分类号： H04J3/06 , H04L25/14
CPC分类号： H04L25/14 , H04J3/0611 , H04J3/0626 , H04J3/1641
摘要： A method and system aggregate data on multiple physically separate lower-speed E1/J1 channels of a communications network to generate higher bandwidth. A high speed data stream is first divided into lower bandwidth channels and transmitted through the network. The data arrives with varying delays depending on the physical characteristics of the network. Low bandwidth channels are aggregated together into a high bandwidth channel by determining the different geographical delay parameters among the lower speed channels, adjusting the transmission delays by alignment circuitry, and then combining the lower speed signals into one high bandwidth channel for the user. The transmission delay adjustment consists in adding a pseudo-random noise pattern to each of the lower bandwidth channels, measuring the time difference among all the channels, and then adjusting the time differences in the received data stream so that the combination of the signals produces a coherent higher bandwidth data stream. Because of the enhanced delay compensation mechanism, there is virtually no distance limitation in the transmission of data and if one of the lower physical telecommunication lines becomes inoperative, bandwidth recovery is provided.
摘要翻译：一种方法和系统在通信网络的多个物理上分离的低速E1 / J1信道上聚合数据，以产生更高的带宽。高速数据流首先被划分为较低带宽信道并通过网络传输。取决于网络的物理特性，数据具有不同的延迟。通过确定低速信道之间的不同地理延迟参数，通过对准电路调整传输延迟，然后将低速信号组合成用于用户的一个高带宽信道，将低带宽信道聚合在一起成为高带宽信道。传输延迟调整包括将伪随机噪声模式添加到每个较低带宽信道，测量所有信道之间的时间差，然后调整接收数据流中的时间差，使得信号的组合产生相干更高带宽的数据流。由于增强的延迟补偿机制，在数据传输中实际上没有距离限制，并且如果较低物理电信线路之一变得不可操作，则提供带宽恢复。

3. 发明授权

US5471581A Elastic configurable buffer for buffering asynchronous data 失效
标题翻译：用于缓冲异步数据的弹性可配置缓冲区
公开(公告)号：US5471581A
公开(公告)日：1995-11-28
申请号：US146770
申请日：1993-06-23
申请人： Jean-Marie Munier , Andre Pauporte , Clement Poiraud
发明人： Jean-Marie Munier , Andre Pauporte , Clement Poiraud
IPC分类号： G06F5/10 , G06F5/16 , G06F13/40 , H04L7/00 , G06F12/00
CPC分类号： G06F5/16 , G06F13/4059 , G06F2205/063
摘要： An elastic buffer is provided between two busses working with independent clocking. The buffer is implemented by a piece of RAM memory (37) partitioned into sectors (41), each of which contains successive memory addresses. Each sector (41), can be alternatively written and read, so that at a given moment, a sector in write mode and a sector in read mode may coexist. Each sector is controlled by a mark flag (MF), a set flag corresponding to a fully written sector, and a reset flag corresponding to a sector that has been read onto the destination bus. The mark flag of each sector is set, respectively reset, upon the event of a move in pointer, respectively move out pointer, reaching the next adjacent sector. For a given elastic buffer size, the size of the sectors (41) and the number of mark flags are adaptable to the specifications of the data flow between the origin and destination busses.
摘要翻译：两台总线之间设有一个弹性缓冲器，可以独立运行。缓冲器由划分成扇区（41）的一块RAM存储器（37）来实现，每个扇区（41）包含连续的存储器地址。可以替代地写入和读取每个扇区（41），使得在给定时刻，写入模式中的扇区和读取模式中的扇区可以共存。每个扇区由标记标志（MF），对应于完全写入的扇区的设置标志以及对应于已经读取到目的地总线上的扇区的复位标志来控制。每个扇区的标记标志分别在指针移动的情况下分别复位，分别移出指针，到达下一个相邻扇区。对于给定的弹性缓冲器大小，扇区（41）的大小和标记标志的数量适用于原始和目的地总线之间的数据流的规范。

4. 发明授权

US5388253A Processing system having device for testing the correct execution of instructions 失效
标题翻译：处理系统具有用于测试指令正确执行的设备
公开(公告)号：US5388253A
公开(公告)日：1995-02-07
申请号：US749848
申请日：1991-08-26
申请人： Michel Geneste , Francois Jacob , Clement Poiraud
发明人： Michel Geneste , Francois Jacob , Clement Poiraud
IPC分类号： G06F9/22 , G06F9/30 , G06F11/10 , G06F11/00
CPC分类号： G06F11/1008 , G06F11/1076 , G06F11/1004
摘要： Processing system for interpreting and carrying out a set of logically related instructions stored into a software program, the execution of a given instruction by the processing system involving the decoding and the execution of a corresponding set of microcommands. The processing system stores a signature portion corresponding to the macrocommand portion of a given instruction which is to be interpreted and executed, and signature data in response to the actual decoding and execution process of the microcommands involved in the execution of the instruction. The processing system further compares the computed signature data with the signature portion in order to detect the occurrence of an error in the decoding and execution process of the given instruction. In one embodiment of the invention, the processing system is such that one instruction is interpreted and executed in one elementary machine cycle. In a second embodiment of the invention, the execution of a given instruction involves the succession of multiple elementary machine cycles.
摘要翻译：用于解释和执行存储到软件程序中的一组逻辑相关指令的处理系统，涉及解码和执行相应的一组微命令的处理系统的给定指令的执行。处理系统存储与要解释和执行的给定指令的宏命令部分对应的签名部分，以及响应于执行指令所涉及的微指令的实际解码和执行处理的签名数据。处理系统还将计算出的签名数据与签名部分进行比较，以便检测给定指令的解码和执行过程中的错误的发生。在本发明的一个实施例中，处理系统使得在一个基本机器周期中解释和执行一个指令。在本发明的第二实施例中，给定指令的执行涉及多个基本机器周期的连续。

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