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1. 发明申请

US20130242985A1 MULTICAST BANDWIDTH MULTIPLICATION FOR A UNIFIED DISTRIBUTED SWITCH 有权
公开(公告)号：US20130242985A1
公开(公告)日：2013-09-19
申请号：US13420180
申请日：2012-03-14
申请人： Claude Basso , Todd A. Greenfield , Philip R. Hillier, III , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool , Bruce M. Walk
发明人： Claude Basso , Todd A. Greenfield , Philip R. Hillier, III , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool , Bruce M. Walk
IPC分类号： H04L12/56
CPC分类号： H04L45/16 , H04L49/201 , H04L49/351 , H04L49/70
摘要： The distributed switch may include a plurality of chips (i.e., sub-switches) on a switch module. These sub-switches may receive from a computing device connected to a Tx/Rx port a multicast data frame (e.g., an Ethernet frame) that designates a plurality of different destinations. Instead of simply using one egress connection interface to forward the copies of the data frame to each of the destinations sequentially, the sub-switch may use a plurality of a connection interfaces to transfer copies of the multicast data frame simultaneously. The port that receives the multicast data frame can borrow the connection interfaces (and associated hardware such as buffers) assigned to these other ports to transmit copies of the multicast data frame simultaneously.

2. 发明授权

US08897301B2 Multicast bandwidth multiplication for a unified distributed switch 有权
标题翻译：统一分布式交换机的组播带宽乘法
公开(公告)号：US08897301B2
公开(公告)日：2014-11-25
申请号：US13420180
申请日：2012-03-14
申请人： Claude Basso , Todd A. Greenfield , Philip R. Hillier, III , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool , Bruce M. Walk
发明人： Claude Basso , Todd A. Greenfield , Philip R. Hillier, III , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool , Bruce M. Walk
IPC分类号： H04L12/28 , H04L12/50 , H04L12/54 , H04J3/24 , H04J3/26 , G06F15/167
CPC分类号： H04L45/16 , H04L49/201 , H04L49/351 , H04L49/70
摘要： The distributed switch may include a plurality of chips (i.e., sub-switches) on a switch module. These sub-switches may receive from a computing device connected to a Tx/Rx port a multicast data frame (e.g., an Ethernet frame) that designates a plurality of different destinations. Instead of simply using one egress connection interface to forward the copies of the data frame to each of the destinations sequentially, the sub-switch may use a plurality of a connection interfaces to transfer copies of the multicast data frame simultaneously. The port that receives the multicast data frame can borrow the connection interfaces (and associated hardware such as buffers) assigned to these other ports to transmit copies of the multicast data frame simultaneously.
摘要翻译：分布式交换机可以包括交换机模块上的多个芯片（即子交换机）。这些子交换机可以从连接到Tx / Rx端口的计算设备接收指定多个不同目的地的多播数据帧（例如，以太网帧）。代替简单地使用一个出口连接接口将数据帧的副本顺序地转发到每个目的地，子交换机可以使用多个连接接口来同时传送多播数据帧的副本。接收组播数据帧的端口可以借用分配给这些其他端口的连接接口（以及相关的硬件，如缓冲区），同时传输组播数据帧的副本。

3. 发明申请

US20090271532A1 Early header CRC in data response packets with variable gap count 审中-公开
标题翻译：数据响应报文中的早期报头CRC可变间隙计数
公开(公告)号：US20090271532A1
公开(公告)日：2009-10-29
申请号：US12108744
申请日：2008-04-24
申请人： Brian D. Allison , Wayne M. Barrett , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool
发明人： Brian D. Allison , Wayne M. Barrett , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool
IPC分类号： G06F13/14
CPC分类号： G06F11/1004
摘要： A method is provided for processing a command issued by a processor over a bus. The method includes (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a header CRC; (3) validating the response packet including the header and the header CRC; (4) loading a timer to run until data required to complete the command is received or the timer expires; and (5) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.
摘要翻译：提供了一种用于处理由总线发出的处理器的命令的方法。该方法包括（1）将命令发送到远程节点以获得完成命令所需的数据; （2）从远程节点接收包括报头和报头CRC的响应分组; （3）验证包括报头和报头CRC的响应报文; （4）加载定时器运行，直到接收完成命令所需的数据或定时器到期; 和（5）在接收完成命令所需的数据之前，安排通过总线将数据返回给处理器。

4. 发明申请

US20090268736A1 Early header CRC in data response packets with variable gap count 审中-公开
标题翻译：数据响应报文中的早期报头CRC可变间隙计数
公开(公告)号：US20090268736A1
公开(公告)日：2009-10-29
申请号：US12108637
申请日：2008-04-24
申请人： Brian D. Allison , Wayne M. Barrett , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool
发明人： Brian D. Allison , Wayne M. Barrett , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool
IPC分类号： H04L12/56
CPC分类号： H04L1/0061 , H04L1/0072 , H04L2001/0094
摘要： A method is provided for processing commands issued by a processor over a bus. The method includes the steps of (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a header CRC; (3) validating the response packet based on the header CRC; and (4) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.
摘要翻译：提供了一种处理由总线发出的命令的方法。该方法包括以下步骤：（1）将命令发送到远程节点以获得对完成命令所需的数据的访问; （2）从远程节点接收包括报头和报头CRC的响应分组; （3）基于报头CRC验证响应分组; 和（4）在接收完成命令所需的数据之前，安排通过总线将数据返回到处理器。

5. 发明申请

US20090268727A1 Early header CRC in data response packets with variable gap count 审中-公开
标题翻译：数据响应报文中的早期报头CRC可变间隙计数
公开(公告)号：US20090268727A1
公开(公告)日：2009-10-29
申请号：US12108735
申请日：2008-04-24
申请人： Brian D. Allison , Wayne M. Barrett , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool
发明人： Brian D. Allison , Wayne M. Barrett , Mark L. Rudquist , Kenneth M. Valk , Brian T. Vanderpool
IPC分类号： H04L12/56
CPC分类号： H04L69/22 , H04L69/324
摘要： A method is provided for processing a command issued by a processor over a bus. The method includes (1) transmitting the command to a remote node to obtain access to data required to complete the command; (2) receiving from the remote node a response packet including a header and a variable gap; and (3) before receiving the data required to complete the command, arranging to return the data to the processor over the bus.
摘要翻译：提供了一种用于处理由总线发出的处理器的命令的方法。该方法包括（1）将命令发送到远程节点以获得完成命令所需的数据; （2）从远程节点接收包括报头和可变间隙的响应分组; 和（3）在接收完成命令所需的数据之前，安排通过总线将数据返回到处理器。

6. 发明申请

US20080244189A1 Method, Apparatus, System and Program Product Supporting Directory-Assisted Speculative Snoop Probe With Concurrent Memory Access 审中-公开
标题翻译：方法，设备，系统和程序产品支持目录辅助的具有并发存储器访问的投机窥探探测器
公开(公告)号：US20080244189A1
公开(公告)日：2008-10-02
申请号：US11693809
申请日：2007-03-30
申请人： Brian D. Allison , Wayne M. Barrett , Philip R. Hillier , Kenneth M. Valk , Brian T. Vanderpool
发明人： Brian D. Allison , Wayne M. Barrett , Philip R. Hillier , Kenneth M. Valk , Brian T. Vanderpool
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F12/0882 , G06F2212/507
摘要： A multiprocessor data processing system includes a memory controller controlling access to a memory subsystem, multiple processor buses coupled to the memory controller, and at least one of multiple processors coupled to each processor bus. In response to receiving a first read request of a first processor via a first processor bus, the memory controller initiates a speculative access to the memory subsystem and a lookup of the target address in a central coherence directory. In response to the central coherence directory indicating that a copy of the target memory block is cached by a second processor, the memory controller transmits a second read request for the target address on a second processor bus. In response to receiving a clean snoop response to the second read request, the memory controller provides to the first processor the target memory block retrieved from the memory subsystem by the speculative access.
摘要翻译：多处理器数据处理系统包括控制对存储器子系统的访问的存储器控制器，耦合到存储器控制器的多个处理器总线以及耦合到每个处理器总线的多个处理器中的至少一个。响应于经由第一处理器总线接收到第一处理器的第一读取请求，存储器控制器启动对存储器子系统的推测访问以及在中央一致性目录中查找目标地址。响应于指示目标存储器块的副本被第二处理器缓存的中央一致性目录，存储器控制器在第二处理器总线上发送针对目标地址的第二读取请求。响应于对第二读取请求接收到干净的窥探响应，存储器控制器通过投机访问向第一处理器提供从存储器子系统检索的目标存储器块。

7. 发明申请

US20080301376A1 Method, Apparatus, and System Supporting Improved DMA Writes 审中-公开
标题翻译：方法，设备和系统支持改进的DMA写入
公开(公告)号：US20080301376A1
公开(公告)日：2008-12-04
申请号：US11756039
申请日：2007-05-31
申请人： Brian D. Allison , David A. Shedivy , Kenneth M. Valk , Brian T. Vanderpool
发明人： Brian D. Allison , David A. Shedivy , Kenneth M. Valk , Brian T. Vanderpool
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： A memory controller receives a stream of DMA write operations and enqueues them in a queue enforcing a First-In First-Out (FIFO) order. Prior to processing a particular DMA write operation, the memory controller acquires coherency ownership of a target memory block and stores the result in a low latency array. In response to acquiring coherency ownership, this low latency array is updated to a coherency state signifying coherency ownership by the memory controller. In a pipelined array access, both the low latency array and the second array are accessed and if the lower latency second array indicates the particular coherency state with no collision indication, the memory controller signals that the particular DMA write operation can be performed, where the signaling occurs prior to results being obtained from the higher latency first array at the normal end of the array access pipeline. In response to the signaling, the memory controller performs an update to the memory subsystem indicated by the particular DMA write operation.
摘要翻译：存储器控制器接收DMA写操作流并将其排入队列中，执行先进先出（FIFO）顺序。在处理特定DMA写入操作之前，存储器控制器获取目标存储器块的一致性所有权并将结果存储在低延迟数组中。响应于获取一致性所有权，该低延迟阵列被更新为表示存储器控制器的一致性所有权的一致性状态。在流水线阵列访问中，访问低延迟阵列和第二阵列，并且如果较低等待时间的第二阵列指示没有冲突指示的特定一致性状态，则存储器控制器指示可以执行特定的DMA写操作，其中信号发生在从阵列访问管道的正常端的较高等待时间第一阵列获得的结果之前。响应于信令，存储器控制器对由特定DMA写操作指示的存储器子系统进行更新。

8. 发明申请

US20090271578A1 Reducing Memory Fetch Latency Using Next Fetch Hint 审中-公开
标题翻译：使用下一个提取提示减少内存提取延迟
公开(公告)号：US20090271578A1
公开(公告)日：2009-10-29
申请号：US12108019
申请日：2008-04-23
申请人： Wayne M. Barrett , Brian T. Vanderpool
发明人： Wayne M. Barrett , Brian T. Vanderpool
IPC分类号： G06F12/00
CPC分类号： G06F12/0215 , G06F12/0862 , G06F2212/6028
摘要： In one aspect, a processor is provided. The processor may include logic, coupled to the processor, and to issue a currently issued memory fetch over a processor bus. The currently issued memory fetch may include a next fetch hint that may include information about a next memory fetch.
摘要翻译：在一个方面，提供一种处理器。处理器可以包括耦合到处理器的逻辑，并且通过处理器总线发布当前发布的存储器提取。当前发行的存储器提取可以包括可以包括关于下一个存储器提取的信息的下一个提取提示。

9. 发明授权

US07519510B2 Derivative performance counter mechanism 失效
标题翻译：衍生性能计数器机制
公开(公告)号：US07519510B2
公开(公告)日：2009-04-14
申请号：US10992444
申请日：2004-11-18
申请人： Brian Lee Koehler , Brian T. Vanderpool
发明人： Brian Lee Koehler , Brian T. Vanderpool
IPC分类号： G06F11/30 , G06F15/00 , G21C17/00
CPC分类号： G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/88 , G06F2201/885
摘要： A circuit and method for using hardware to calculate a first derivative of the number of performance events that occur in a microprocessor during a predetermined period of time. This first derivative indicates a frequency of such performance events, which can be used as either a predictor of future problems or needs, or may be used to invoke a corrective action.
摘要翻译：一种用于使用硬件来计算在预定时间段内在微处理器中发生的性能事件数量的一阶导数的电路和方法。这种一阶导数表示这种性能事件的频率，可以用作未来问题或需求的预测器，或者可以用于调用纠正措施。

10. 发明申请

US20080307169A1 Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory 审中-公开
标题翻译：方法，设备，系统和程序产品支持改进的部署目录的访问延迟
公开(公告)号：US20080307169A1
公开(公告)日：2008-12-11
申请号：US11758851
申请日：2007-06-06
申请人： Duane Arlyn Averill , Jonathon C. Skarphol , Brian T. Vanderpool
发明人： Duane Arlyn Averill , Jonathon C. Skarphol , Brian T. Vanderpool
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F2212/1016
摘要： A data processing system includes a coherence directory having a prefetch sector cache and a memory directory array containing a plurality of sectored entries. According to one method, in response to receiving a first directory lookup request specifying a first target address, an entry associated with the target address is accessed in the memory directory array. In response to the access, the coherence directory returns, as a result of the first directory lookup request, contents of a first sector that is identified by the target address as a requested sector. The coherence directory also caches contents of a second sector of the multiple sectors that is a non-requested sector for the first directory lookup request in a prefetch sector cache. In response to receiving a subsequent second directory lookup request specifying a second target address that identifies the second sector as a requested sector, the coherence directory accesses the contents of the second sector in the sector prefetch cache and returns the contents of the second sector as a result of the second directory lookup request.
摘要翻译：数据处理系统包括具有预取扇区高速缓存的同步目录和包含多个扇区条目的存储器目录阵列。根据一种方法，响应于接收到指定第一目标地址的第一目录查找请求，在存储器目录数组中访问与目标地址相关联的条目。响应于访问，相干目录作为第一目录查找请求的结果返回由目标地址识别为请求扇区的第一扇区的内容。相干目录还将作为第一目录查找请求的非请求扇区的多个扇区的第二扇区的内容缓存在预取扇区高速缓存中。响应于接收指定识别第二扇区作为所请求扇区的第二目标地址的后续第二目录查找请求，所述相干目录访问扇区预取高速缓存中的第二扇区的内容，并将第二扇区的内容返回为第二个目录查询请求的结果。

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