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1. 发明申请

US20130339573A1 OPTIMIZING WRITE PERFORMANCE TO FLASH MEMORY 审中-公开
标题翻译：优化写入闪存的写入性能
公开(公告)号：US20130339573A1
公开(公告)日：2013-12-19
申请号：US13524484
申请日：2012-06-15
申请人： Clark A. Anderson , Edward W. Chencinski , Jon S. Entwistle , Adrian C. Gerhard , Thomas J. Griffin , Charles E. Mari , Kenneth J. Oakes , Steven M. Partlow , Peter G. Sutton , Elpida Tzortzatos , Dustin J. VanStee
发明人： Clark A. Anderson , Edward W. Chencinski , Jon S. Entwistle , Adrian C. Gerhard , Thomas J. Griffin , Charles E. Mari , Kenneth J. Oakes , Steven M. Partlow , Peter G. Sutton , Elpida Tzortzatos , Dustin J. VanStee
IPC分类号： G06F12/02
CPC分类号： G06F12/08 , G06F2212/214
摘要： Embodiments relate to optimizing write performance of a flash device. Aspects include receiving a request to evict a plurality of pages from a main memory and determining a block size for the flash device. Aspects also include grouping the plurality of pages from the main memory into a move specification block, wherein a size of the move specification block is the block size and writing the move specification block to the flash device. The block size being determined based on one or more operational characteristics of the flash device.
摘要翻译：实施例涉及优化闪存设备的写入性能。方面包括接收从主存储器驱逐多个页面并确定闪存设备的块大小的请求。方面还包括将来自主存储器的多个页面分组为移动指定块，其中移动指定块的大小是块大小并将移动指定块写入闪存设备。块尺寸是基于闪光装置的一个或多个操作特性确定的。

2. 发明申请

US20130339784A1 ERROR RECOVERY IN REDUNDANT STORAGE SYSTEMS 审中-公开
标题翻译：冗余存储系统中的错误恢复
公开(公告)号：US20130339784A1
公开(公告)日：2013-12-19
申请号：US13524719
申请日：2012-06-15
申请人： Craig A. Bickelman , Brian Bowles , David D. Cadigan , Edward W. Chencinski , Robert E. Galbraith , Adam J. McPadden , Kenneth J. Oakes , Peter K. Szwed
发明人： Craig A. Bickelman , Brian Bowles , David D. Cadigan , Edward W. Chencinski , Robert E. Galbraith , Adam J. McPadden , Kenneth J. Oakes , Peter K. Szwed
IPC分类号： G06F11/14
CPC分类号： G06F11/1092 , G06F11/2082
摘要： Embodiments relate to providing error recovery in a storage system that utilizes data redundancy. An aspect of the invention includes monitoring plurality of storage devices of the storage system and determining that one of the plurality of storage devices has failed based on the monitoring. Another aspect of includes suspending data reads and writes to the failed storage device and determining that the failed storage device is recoverable. Based on determining that the failed storage device is recoverable, initiating a rebuilding recovery process of the failed storage device based on determining that the failed storage device is recoverable and restoring data reads and writes to the failed storage device upon completion of the rebuilding recovery process.
摘要翻译：实施例涉及在利用数据冗余的存储系统中提供错误恢复。本发明的一个方面包括监视存储系统的多个存储设备，并且基于监视来确定多个存储设备中的一个存储设备已经发生故障。另一方面包括暂停对故障存储设备的数据读写，并确定故障存储设备是可恢复的。基于确定故障存储设备是可恢复的，基于确定故障存储设备是可恢复的，启动故障存储设备的重建恢复过程，并且在重建恢复过程完成时恢复对故障存储设备的数据读取和写入。

3. 发明授权

US08880956B2 Facilitating processing in a communications environment using stop signaling 有权
标题翻译：在通信环境中使用停止信号促进处理
公开(公告)号：US08880956B2
公开(公告)日：2014-11-04
申请号：US13151119
申请日：2011-06-01
申请人： Edward W. Chencinski , Michael Jung , Martin Rehm , Philip A. Sciuto
发明人： Edward W. Chencinski , Michael Jung , Martin Rehm , Philip A. Sciuto
IPC分类号： G06F11/00
CPC分类号： H04L41/0654 , H04L41/069
摘要： Processing, such as debug and/or recovery processing, within a communications environment is facilitated. Responsive to detecting an event, a stop signal is propagated through a communications network of the communications environment, and each network element that receives the stop signal, transmits the signal to its neighbors (if any), and then performs an action depending on its specific programming. The action can be to take no action, perform a debugging action or perform a recovery action. The elements that receive the signal and perform the same action as other elements form a coordinated network providing a coordinated result.
摘要翻译：促进在通信环境内的处理，例如调试和/或恢复处理。响应于检测事件，通过通信环境的通信网络传播停止信号，并且接收停止信号的每个网络单元将信号发送到其邻居（如果有的话），然后根据其特定的编程。该操作可以不采取任何行动，执行调试操作或执行恢复操作。接收信号并执行与其他元素相同的动作的元素形成协调的网络，提供协调的结果。

4. 发明授权

US08582778B2 Integrated key server 有权
标题翻译：集成密钥服务器
公开(公告)号：US08582778B2
公开(公告)日：2013-11-12
申请号：US13150420
申请日：2011-06-01
申请人： Edward W. Chencinski , James R. Coon , John C. Dayka , Steven G. Glassen , Richard J. Gusefski , Michael J. Jordan , Marco Kraemer , Thomas B. Mathias , Peter K. Szwed , Garry J. Sullivan , Klaus Werner
发明人： Edward W. Chencinski , James R. Coon , John C. Dayka , Steven G. Glassen , Richard J. Gusefski , Michael J. Jordan , Marco Kraemer , Thomas B. Mathias , Peter K. Szwed , Garry J. Sullivan , Klaus Werner
IPC分类号： G06F21/00
CPC分类号： H04L9/0822 , H04L9/0825 , H04L9/0877 , H04L9/0894
摘要： A computer program product for integrated key serving is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes using a smart card of two or more smart cards with a support element of two or more support elements to create an encryption key and storing the encryption key in an encrypted file that can only be decrypted by the smart card and the support element used to create the encryption key.
摘要翻译：提供一种用于集成密钥服务的计算机程序产品。计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。该方法包括使用具有两个或更多个支持元件的支持元件的两个或多个智能卡的智能卡来创建加密密钥，并将加密密钥存储在只能由智能卡和支持元件解密的加密文件中用于创建加密密钥。

5. 发明申请

US20120308011A1 INTEGRATED KEY SERVER 有权
标题翻译：集成关键服务器
公开(公告)号：US20120308011A1
公开(公告)日：2012-12-06
申请号：US13150420
申请日：2011-06-01
申请人： Edward W. Chencinski , James R. Coon , John C. Dayka , Steven G. Glassen , Richard J. Gusefski , Michael J. Jordan , Marco Kraemer , Thomas B. Mathias , Peter K. Szwed , Garry J. Sullivan , Klaus Werner
发明人： Edward W. Chencinski , James R. Coon , John C. Dayka , Steven G. Glassen , Richard J. Gusefski , Michael J. Jordan , Marco Kraemer , Thomas B. Mathias , Peter K. Szwed , Garry J. Sullivan , Klaus Werner
IPC分类号： H04L9/08 , H04L9/00
CPC分类号： H04L9/0822 , H04L9/0825 , H04L9/0877 , H04L9/0894
摘要： A computer program product for integrated key serving is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes using a smart card of two or more smart cards with a support element of two or more support elements to create an encryption key and storing the encryption key in an encrypted file that can only be decrypted by the smart card and the support element used to create the encryption key.
摘要翻译：提供一种用于集成密钥服务的计算机程序产品。计算机程序产品包括可由处理电路读取的有形存储介质，并且存储由处理电路执行以执行方法的指令。该方法包括使用具有两个或更多个支持元件的支持元件的两个或多个智能卡的智能卡来创建加密密钥，并将加密密钥存储在只能由智能卡和支持元素解密的加密文件中用于创建加密密钥。

6. 发明申请

US20120311133A1 FACILITATING PROCESSING IN A COMMUNICATIONS ENVIRONMENT USING STOP SIGNALING 有权
标题翻译：通信停止信号通信环境中的加速处理
公开(公告)号：US20120311133A1
公开(公告)日：2012-12-06
申请号：US13151119
申请日：2011-06-01
申请人： Edward W. Chencinski , Michael Jung , Martin Rehm , Philip A. Sciuto
发明人： Edward W. Chencinski , Michael Jung , Martin Rehm , Philip A. Sciuto
IPC分类号： G06F15/173
CPC分类号： H04L41/0654 , H04L41/069
摘要： Processing, such as debug and/or recovery processing, within a communications environment is facilitated. Responsive to detecting an event, a stop signal is propagated through a communications network of the communications environment, and each network element that receives the stop signal, transmits the signal to its neighbors (if any), and then performs an action depending on its specific programming. The action can be to take no action, perform a debugging action or perform a recovery action. The elements that receive the signal and perform the same action as other elements form a coordinated network providing a coordinated result.
摘要翻译：促进在通信环境内的处理，例如调试和/或恢复处理。响应于检测事件，通过通信环境的通信网络传播停止信号，并且接收停止信号的每个网络单元将信号发送到其邻居（如果有的话），然后根据其特定的编程。该操作可以不采取任何行动，执行调试操作或执行恢复操作。接收信号并执行与其他元素相同的动作的元素形成协调的网络，提供协调的结果。

7. 发明授权

US06963977B2 Circuits and methods for modular exponentiation 失效
标题翻译：用于模幂运算的电路和方法
公开(公告)号：US06963977B2
公开(公告)日：2005-11-08
申请号：US09740411
申请日：2000-12-19
申请人： Chin-Long Chen , Edward W. Chencinski , Vincenzo Condorelli , Leonard L. Fogell , Samir K. Patel
发明人： Chin-Long Chen , Edward W. Chencinski , Vincenzo Condorelli , Leonard L. Fogell , Samir K. Patel
IPC分类号： G06F7/72 , H04K1/00 , H04L9/00
CPC分类号： G06F7/723
摘要： The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity. While the present disclosure is directed to a complex system which includes a number of features, the present application is particularly directed to circuits and methods for carrying out modular exponentiation.
摘要翻译：在公开密钥加密和解密系统中使用的模幂运算功能是在独立的引擎中实现的，该独立引擎在其核心模乘法电路中分两个阶段工作，这两个阶段共享重叠的硬件结构。将硬件结构中的大阵列用于乘法和加法分割成更小的结构导致乘法器设计，其包括以链式方式链接在一起的一系列几乎相同的处理元件。作为分段处理元件的两相操作和链接在一起的结果，整体结构以流水线方式操作以提高生产量和速度。链式处理元件被构造成提供具有用于处理模量因子的单独部件的可分隔链。在这种模式下，该系统特别适用于利用中国剩余定理的特征进行快速求幂运算。还提供校验和机制以确保精确的操作而不影响速度并且不会显着增加复杂性。虽然本公开涉及包括许多特征的复杂系统，但是本申请特别涉及用于执行模幂运算的电路和方法。

8. 发明授权

US08880957B2 Facilitating processing in a communications environment using stop signaling 有权
公开(公告)号：US08880957B2
公开(公告)日：2014-11-04
申请号：US13459162
申请日：2012-04-28
申请人： Edward W. Chencinski , Michael Jung , Martin Rehm , Philip A. Sciuto
发明人： Edward W. Chencinski , Michael Jung , Martin Rehm , Philip A. Sciuto
IPC分类号： G06F11/00
CPC分类号： H04L41/0654 , H04L41/069
摘要： Processing, such as debug and/or recovery processing, within a communications environment is facilitated. Responsive to detecting an event, a stop signal is propagated through a communications network of the communications environment, and each network element that receives the stop signal, transmits the signal to its neighbors (if any), and then performs an action depending on its specific programming. The action can be to take no action, perform a debugging action or perform a recovery action. The elements that receive the signal and perform the same action as other elements form a coordinated network providing a coordinated result.

9. 发明授权

US5590309A Storage protection cache and backing storage having system control element data cache pipeline and storage protection bits in a stack array with a stack directory for the stack array 失效
标题翻译：存储保护缓存和备份存储，具有堆栈数组中的系统控制元素数据高速缓存流水线和存储保护位，并具有堆栈数组的堆栈目录
公开(公告)号：US5590309A
公开(公告)日：1996-12-31
申请号：US222191
申请日：1994-04-01
申请人： Edward W. Chencinski , Jeffrey C. Bixler , Neal T. Christensen
发明人： Edward W. Chencinski , Jeffrey C. Bixler , Neal T. Christensen
IPC分类号： G06F12/08
CPC分类号： G06F12/0875
摘要： A high performance cache and storage control and management scheme for storage protection (SP) bits. The SP bits of interest are "key", "reference" and "change" bits which are architected to prevent unauthorized access to storage and to allow the efficient paging of main storage data. Access to this SP cache (SPC) is achieved via a 5 cycle pipeline. This SPC pipeline will deliver information back to the requestor as well as manage updates to the SPC on cache hits. The pipeline leads to a request stack in the SP storage (SPS) controller. This SPS stack manages the request during its execution in the SPS and the subsequent putaway of fetch results in the SPC. The organization of the cache along with its integration of directory information allow for the utilization of the unique properties of SP data to provide an extremely fast and efficient cache management scheme.
摘要翻译：用于存储保护（SP）位的高性能缓存和存储控制和管理方案。感兴趣的SP位是“密钥”，“参考”和“改变”位，其被构造为防止未经授权的访问存储并且允许主存储数据的有效寻呼。通过5个循环管道实现对SP SP（SPC）的访问。此SPC管道将信息传回请求者，并在缓存命中时管理SPC的更新。管道导致SP存储（SPS）控制器中的请求堆栈。该SPS堆栈在SPS执行期间管理该请求，随后在SPC中提取结果。缓存的组织以及目录信息的集成允许利用SP数据的独特属性来提供非常快速和高效的缓存管理方案。

10. 发明授权

US08787155B2 Sideband error signaling 失效
标题翻译：边带错误信号
公开(公告)号：US08787155B2
公开(公告)日：2014-07-22
申请号：US13151107
申请日：2011-06-01
申请人： Edward W. Chencinski , Michael Jung , Martin Rehm , Philip A. Sciuto
发明人： Edward W. Chencinski , Michael Jung , Martin Rehm , Philip A. Sciuto
IPC分类号： H04L1/00 , H04L29/14 , H04L12/24 , H04L1/24
CPC分类号： H04L29/14 , H04L1/24 , H04L41/0659 , H04L69/40
摘要： Fast error reporting is provided in networks that have an architected delayed error reporting capability. Errors are detected and reported without having to wait for a timeout period to expire. Further, failures of other components caused by the delay are avoided, since the delay is bypassed.
摘要翻译：在具有架构延迟错误报告功能的网络中提供快速错误报告。错误检测和报告，而不必等待超时期限到期。此外，由于延迟被绕过而避免了由延迟引起的其它部件的故障。

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