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1. 发明授权

US5590309A Storage protection cache and backing storage having system control element data cache pipeline and storage protection bits in a stack array with a stack directory for the stack array 失效
标题翻译：存储保护缓存和备份存储，具有堆栈数组中的系统控制元素数据高速缓存流水线和存储保护位，并具有堆栈数组的堆栈目录
公开(公告)号：US5590309A
公开(公告)日：1996-12-31
申请号：US222191
申请日：1994-04-01
申请人： Edward W. Chencinski , Jeffrey C. Bixler , Neal T. Christensen
发明人： Edward W. Chencinski , Jeffrey C. Bixler , Neal T. Christensen
IPC分类号： G06F12/08
CPC分类号： G06F12/0875
摘要： A high performance cache and storage control and management scheme for storage protection (SP) bits. The SP bits of interest are "key", "reference" and "change" bits which are architected to prevent unauthorized access to storage and to allow the efficient paging of main storage data. Access to this SP cache (SPC) is achieved via a 5 cycle pipeline. This SPC pipeline will deliver information back to the requestor as well as manage updates to the SPC on cache hits. The pipeline leads to a request stack in the SP storage (SPS) controller. This SPS stack manages the request during its execution in the SPS and the subsequent putaway of fetch results in the SPC. The organization of the cache along with its integration of directory information allow for the utilization of the unique properties of SP data to provide an extremely fast and efficient cache management scheme.
摘要翻译：用于存储保护（SP）位的高性能缓存和存储控制和管理方案。感兴趣的SP位是“密钥”，“参考”和“改变”位，其被构造为防止未经授权的访问存储并且允许主存储数据的有效寻呼。通过5个循环管道实现对SP SP（SPC）的访问。此SPC管道将信息传回请求者，并在缓存命中时管理SPC的更新。管道导致SP存储（SPS）控制器中的请求堆栈。该SPS堆栈在SPS执行期间管理该请求，随后在SPC中提取结果。缓存的组织以及目录信息的集成允许利用SP数据的独特属性来提供非常快速和高效的缓存管理方案。

2. 发明授权

US4271468A Multiprocessor mechanism for handling channel interrupts 失效
公开(公告)号：US4271468A
公开(公告)日：1981-06-02
申请号：US91902
申请日：1979-11-06
申请人： Neal T. Christensen , William C. Van Loo , Robert H. Werner , Joseph A. Wetzel , Carl Zeitler, Jr.
发明人： Neal T. Christensen , William C. Van Loo , Robert H. Werner , Joseph A. Wetzel , Carl Zeitler, Jr.
IPC分类号： G06F13/14 , G06F9/46 , G06F9/48 , G06F13/26 , G06F15/16 , G06F15/177 , G06F15/00
CPC分类号： G06F13/26
摘要： The disclosure relates to multiprocessor handling of plural queues of pending I/O interrupt requests (I/O IRs) in a main storage (MS) shared by plural central processors (CPs). An input/output processor (IOP) inserts I/O IR entries onto the queues in accordance with the type of interrupt. The entries in the queues are only removed by the CPs, after their selection by a system controller (SC) for execution of an interruption handling program.An I/O interrupt pending register in I/O interrupt controller circuits in the SC is used in selecting CPs to handle the I/O IRs on the queues. The bit positions in the pending register are respectively assigned to the I/O IR queues in MS, and the order of the bit positions determines the priority among the queues for CP handling. An I/O IR command from the IOP to the SC sets a corresponding queue bit position in the pending register and controls the addition of an entry on the corresponding queue in MS. If a bit is set to one, the corresponding queue is non-empty; if set to zero, the queue is empty.A broadcast bus connects the outputs of the bit positions of the pending register to each of the CPs.In each CP, acceptance determining circuits connect to the broadcast bus and accept the highest-priority-unmask non-empty-state bit position being broadcast. From this, the CP sends the SC an accepted queue identifier signal and an accept signal when the CP is in an interruptable state. The CP also sends to the SC a wait state signal if the CP is then in wait state.Selection determining circuits in the SC receive the accept, wait (if any), and queue identifier signals from all accepting CPs and select one accepting CP per accepted queue at any one time. The selection circuits can perform the selection of plural CPs in parallel, and send a select signal to each selected CP.An inhibit register in the interrupt controller in the SC inhibits selected bits on the broadcast bus to all CPs except the selected CP for the selected queue identifier. The inhibit on any bit is removed when the selected CP ends its acceptance of the corresponding queue, so that any CP can select the next entry on the corresponding queue.When any selected CP finds it has emptied a queue, it activates a reset line to the SC which resets the corresponding bit in the pending register to indicate the empty state.

3. 发明授权

US4916703A Handling errors in the C bit of a storage key 失效
标题翻译：处理存储密钥的C位中的错误
公开(公告)号：US4916703A
公开(公告)日：1990-04-10
申请号：US276736
申请日：1988-11-28
申请人： Neal T. Christensen , Steven T. Comfort , Robert J. Hurban , Bruce L. McGilvray , Arthur J. Sutton , James R. Urquhart , David R. Willoughby
发明人： Neal T. Christensen , Steven T. Comfort , Robert J. Hurban , Bruce L. McGilvray , Arthur J. Sutton , James R. Urquhart , David R. Willoughby
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/00 , G06F11/10
摘要： A method of handling errors in the C bit of a storage key by modifying the INSERT STORAGE KEY (ISK) and the RESET REFERENCE BIT (RRB) instructions. If an error is found in the C bit during the execution of these instructions, microcode is instructed to refresh the C bit. The C bit is interrogated a second time to determine if the refreshed C bit is still in error. If the refreshed C bit is not in error a second time, then the first error was caused by a soft or transient error, and the instruction is continued. If the refreshed C bit is in error a second time then the first and second errors were caused by a permanent error such as a stuck bit, and a system recovery machine check error is generated. The handling of C bit errors is thus done in a dynamic fashion as the instructions are executed.

4. 发明授权

US5490261A Interlock for controlling processor ownership of pipelined data for a store in cache 失效
标题翻译：用于控制缓存中存储的流水线数据的处理器所有权的联锁
公开(公告)号：US5490261A
公开(公告)日：1996-02-06
申请号：US680176
申请日：1991-04-03
申请人： Bradford M. Bean , Anne E. Bierce , Neal T. Christensen , Leo J. Clark , Steven T. Comfort , Christine C. Jones , Pak-Kin Mak
发明人： Bradford M. Bean , Anne E. Bierce , Neal T. Christensen , Leo J. Clark , Steven T. Comfort , Christine C. Jones , Pak-Kin Mak
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0811
摘要： Insures data integrity in process ownership indications by providing an ownership interlock on the data units in a pipeline to a store-in type of cache. An ownership interlock prevents any processor ownership change to occur (i.e. exclusive or readonly ownership) for a cache data unit until all outstanding stores have been made in the cache data unit, after which the ownership may be changed. An ownership change may be signalled by a cross-invalidate (XI) signal to a processor. Outstanding stores are received by the pipeline after the stores are completed by a processor, and the outstanding stores output from the pipeline into a store-in cache. A continuous flow of stores is enabled into and out of the pipeline to expedite a change of ownership requested of a data unit in the cache. The continuous flow avoids having to stop a processor from putting stores into the pipeline and avoids forcing all outstanding stores out of the pipeline into the cache before indicating a change of processor ownership.
摘要翻译：通过在流水线中的数据单元上提供所有权互锁到存储型缓存来保护进程所有权指示中的数据完整性。所有权互锁防止对高速缓存数据单元发生任何处理器所有权改变（即，独占或只读所有权），直到所有未完成的存储已经在高速缓存数据单元中进行，之后可以改变所有权。所有权变更可以通过交叉无效（XI）信号发送给处理器。在存储由处理器完成之后，流水线接收到未完成的存储，并且从流水线输出的未完成存储到存储缓存中。连续的商店流程被启用进出管道，以加快对高速缓存中数据单元所需的所有权的更改。连续流程避免了停止处理器将存储放入流水线中，并避免在指示处理器所有权的更改之前将所有未完成的存储从管道中强制进入高速缓存。

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