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1. 发明授权

US08659340B2 Tunable voltage-controlled pseudo-resistor 失效
标题翻译：可调电压控制的伪电阻
公开(公告)号：US08659340B2
公开(公告)日：2014-02-25
申请号：US13421376
申请日：2012-03-15
申请人： Muh-Tian Shiue , Kai-Wen Yao , Cihun-Siyong Gong
发明人： Muh-Tian Shiue , Kai-Wen Yao , Cihun-Siyong Gong
IPC分类号： H03L5/00
CPC分类号： H03H11/53
摘要： A tunable voltage-controlled pseudo-resistor structure, comprising: a symmetric PMOS transistor circuit and an auto-tuning circuit connected in series. Input of the auto-tuning circuit is connected to a central position Vf of the PMOS transistor circuit having its output Vg, with its purpose of keeping Vg−Vf at a constant value. The PMOS transistor circuit may produce body effect through various different bulk voltages. Through the auto-tuning circuit, Vg and Vf are kept constant to make current of transistor to produce compensation effect, such that regardless of Va>Vb or Va
摘要翻译：一种可调电压控制的伪电阻器结构，包括：对称PMOS晶体管电路和串联连接的自动调谐电路。自调谐电路的输入连接到具有其输出Vg的PMOS晶体管电路的中心位置Vf，其目的是将Vg-Vf保持在恒定值。 PMOS晶体管电路可以通过各种不同的体电压产生身体效应。通过自调谐电路，Vg和Vf保持恒定，以使晶体管的电流产生补偿效果，使得不管Va> Vb或Va

2. 发明申请

US20100182079A1 Low Complexity and Low Power Phase Shift Keying Demodulator Structure 有权
标题翻译：低复杂度和低功耗相移键控解调器结构
公开(公告)号：US20100182079A1
公开(公告)日：2010-07-22
申请号：US12355812
申请日：2009-01-19
申请人： Muh-Tian Shiue , Cihun-Siyong Gong , Kai-Wen Yao
发明人： Muh-Tian Shiue , Cihun-Siyong Gong , Kai-Wen Yao
IPC分类号： H03D3/00
CPC分类号： H03D3/006
摘要： A low complexity and low power phase shift keying demodulator structure comprises: a digitizer, a phase-transition-independent carrier clock extractor, a binary correlater, a delay element, and a sampler; wherein the digitizer digitizes a BPSK signal for an output waveform, the phase-transition-independent carrier clock extractor detects the phase transition on the output of the digitizer and produces a carrier clock signal, the binary correlater has correlated processes to the output signal of the digitizer and carrier clock signal obtained from the phase-transition-independent carrier clock extractor, the sampler samples the signal from the binary correlater according to the signal from the delay element in order to finish the demodulation with only small capacitance.
摘要翻译：低复杂度和低功率相移键控解调器结构包括：数字转换器，相移独立载波时钟提取器，二进制相关器，延迟元件和采样器; 其中数字转换器对输出波形的BPSK信号进行数字化，相变独立载波时钟提取器检测数字转换器的输出上的相位转换并产生载波时钟信号，二进制相关器具有与数字转换器和载波时钟信号，采样器根据来自延迟元件的信号对来自二进制相关器的信号进行采样，以完成仅具有小电容的解调。

3. 发明授权

US07911266B2 Low complexity and low power phase shift keying demodulator structure 有权
标题翻译：低复杂度和低功耗相移键控解调器结构
公开(公告)号：US07911266B2
公开(公告)日：2011-03-22
申请号：US12355812
申请日：2009-01-19
申请人： Cihun-Siyong Gong , Muh-Tian Shiue , Kai-Wen Yao
发明人： Cihun-Siyong Gong , Muh-Tian Shiue , Kai-Wen Yao
IPC分类号： H03D3/00
CPC分类号： H03D3/006
摘要： A low complexity and low power phase shift keying demodulator structure includes a digitizer, a phase-transition-independent carrier clock extractor, a binary correlater, a delay element, and a sampler. The digitizer digitizes a BPSK signal for an output waveform. The phase-transition-independent carrier clock extractor detects the phase transition on the output of the digitizer and produces a carrier clock signal. The binary correlater has correlated processes to the output signal of the digitizer and carrier clock signal obtained from the phase-transition-independent carrier clock extractor. The sampler samples the signal from the binary correlater according to the signal from the delay element in order to finish the demodulation with only a small capacitance.
摘要翻译：低复杂度和低功率相移键控解调器结构包括数字转换器，相移独立载波时钟提取器，二进制相关器，延迟元件和采样器。数字转换器将输出波形的BPSK信号数字化。相位转移无关载波时钟提取器检测数字转换器输出端的相位转换，产生载波时钟信号。二进制相关器具有与数字转换器的输出信号和从相变非独立载波时钟提取器获得的载波时钟信号的相关处理。采样器根据来自延迟元件的信号对来自二进制相关器的信号进行采样，以完成仅具有小电容的解调。

4. 发明申请

US20110007556A1 SRAM Architecture 有权
标题翻译： SRAM架构
公开(公告)号：US20110007556A1
公开(公告)日：2011-01-13
申请号：US12499135
申请日：2009-07-08
申请人： Cihun-Siyong Gong , Ci-Tong Hong , Muh-Tian Shiue , Kai-Wen Yao
发明人： Cihun-Siyong Gong , Ci-Tong Hong , Muh-Tian Shiue , Kai-Wen Yao
IPC分类号： G11C11/00 , G11C7/00 , G11C5/14
CPC分类号： G11C11/413
摘要： A SRAM architecture comprises a read/write control signal, a read/write control transistor block, an equalize transistor block, a 6-T SRAM cell, a sense amplifier block, a column selection transistor block and a write driver. The 6-T SRAM cell can store and write data. The sense amplifier block is used to read out the data stored in the 6-T SRAM cell correctly when the SRAM architecture performs a read operation and makes bit lines BL (bit line) and BLB( bitline) produce a minimum voltage difference. The column selection transistor block is used to select a column that the data is written in and read out stored in. The write driver is used to perform a write operation to the 6-T SRAM cell of the column. The SRAM architecture can effectively increase the read SNM and dramatically reduce the power consumption.
摘要翻译： SRAM架构包括读/写控制信号，读/写控制晶体管块，均衡晶体管块，6-T SRAM单元，读出放大器块，列选择晶体管块和写驱动器。 6-T SRAM单元可以存储和写入数据。当SRAM架构执行读操作并使位线BL（位线）和BLB（位线）产生最小电压差时，读出放大器模块用于读出存储在6-T SRAM单元中的数据。列选择晶体管块用于选择数据被写入并读出存储的列。写驱动器用于对列的6-T SRAM单元执行写操作。 SRAM架构可以有效地增加读取的SNM并显着降低功耗。

5. 发明授权

US08009462B2 SRAM architecture 有权
标题翻译： SRAM架构
公开(公告)号：US08009462B2
公开(公告)日：2011-08-30
申请号：US12499135
申请日：2009-07-08
申请人： Cihun-Siyong Gong , Ci-Tong Hong , Muh-Tian Shiue , Kai-Wen Yao
发明人： Cihun-Siyong Gong , Ci-Tong Hong , Muh-Tian Shiue , Kai-Wen Yao
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C11/413
摘要： A SRAM architecture includes a read/write control signal, a read/write control transistor block, an equalize transistor block, a 6-T SRAM cell, a sense amplifier block, a column selection transistor block and a write driver. The 6-T SRAM cell can store and write data. The sense amplifier block is used to read out the data stored in the 6-T SRAM cell correctly when the SRAM architecture performs a read operation and makes bit lines BL (bit line) and BLB( bitline) produce a minimum voltage difference. The column selection transistor block is used to select a column that the data is written in and read out. The write driver is used to perform a write operation to the 6-T SRAM cell of the column. The SRAM architecture can effectively increase the read SNM and dramatically reduce the power consumption.
摘要翻译： SRAM架构包括读/写控制信号，读/写控制晶体管块，均衡晶体管块，6-T SRAM单元，读出放大器块，列选择晶体管块和写驱动器。 6-T SRAM单元可以存储和写入数据。当SRAM架构执行读操作并使位线BL（位线）和BLB（位线）产生最小电压差时，读出放大器模块用于读出存储在6-T SRAM单元中的数据。列选择晶体管块用于选择数据被写入并读出的列。写驱动器用于对列的6-T SRAM单元执行写操作。 SRAM架构可以有效地增加读取的SNM并显着降低功耗。

6. 发明授权

US07746117B2 Complementary energy path adiabatic logic 有权
标题翻译：互补能量路径绝热逻辑
公开(公告)号：US07746117B2
公开(公告)日：2010-06-29
申请号：US12236571
申请日：2008-09-24
申请人： Ci-Tong Hong , Cihun-Siyong Gong , Chun-Hsien Su , Muh-Tian Shiue , Kai-Wen Yao
发明人： Ci-Tong Hong , Cihun-Siyong Gong , Chun-Hsien Su , Muh-Tian Shiue , Kai-Wen Yao
IPC分类号： H03K19/096
CPC分类号： H03K19/0019 , H03K19/096 , H03K19/0963
摘要： A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-type MOS transistors and additional P-type and N-type MOS transistors, with each of the transistors involved in the power clock network acting as an active diode.
摘要翻译：互补能量路径绝热逻辑（CEPAL）包括评估网络和电源时钟网络。评估网络是由P型MOS晶体管和N型MOS晶体管组成的逻辑电路。功率时钟网络包括P型和N型MOS晶体管和附加的P型和N型MOS晶体管，其中涉及功率时钟网络的每个晶体管用作有源二极管。

7. 发明申请

US20100073029A1 Complementary Energy Path Adiabatic Logic 有权
标题翻译：互补能量路径绝热逻辑
公开(公告)号：US20100073029A1
公开(公告)日：2010-03-25
申请号：US12236571
申请日：2008-09-24
申请人： Ci-Tong Hong , Cihun-Siyong Gong , Chun-Hsien Su , Muh-Tian Shiue , Kai-Wen Yao
发明人： Ci-Tong Hong , Cihun-Siyong Gong , Chun-Hsien Su , Muh-Tian Shiue , Kai-Wen Yao
IPC分类号： H03K19/0948 , H03K19/096
CPC分类号： H03K19/0019 , H03K19/096 , H03K19/0963
摘要： A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-type MOS transistors and additional P-type and N-type MOS transistors, with each of the transistors involved in the power clock network acting as an active diode.
摘要翻译：互补能量路径绝热逻辑（CEPAL）包括评估网络和电源时钟网络。评估网络是由P型MOS晶体管和N型MOS晶体管组成的逻辑电路。功率时钟网络包括P型和N型MOS晶体管和附加的P型和N型MOS晶体管，其中涉及功率时钟网络的每个晶体管用作有源二极管。

8. 发明申请

US20100239033A1 Joint carrier synchronization and channel equalization method for OFDM systems 有权
标题翻译： OFDM系统的联合载波同步和信道均衡方法
公开(公告)号：US20100239033A1
公开(公告)日：2010-09-23
申请号：US12585220
申请日：2009-09-09
申请人： Muh-Tian Shiue , Chih-Feng Wu , Chorng-Kuang Wang
发明人： Muh-Tian Shiue , Chih-Feng Wu , Chorng-Kuang Wang
IPC分类号： H04L27/28
CPC分类号： H04L27/2672 , H04L25/03273 , H04L27/266 , H04L2025/03414 , H04L2025/0377
摘要： A joint carrier synchronization and channel equalization method for OFDM systems, that is suitable for use in a receiver of said orthogonal frequency division multiplexer (OFDM) systems, comprising the following steps: firstly, receiving a reception signal sample of an OFDM symbol, and obtaining simultaneously a phase error and a gain error on each sub-channel in a frequency domain, through outputting a sub-channel signal on each said sub-channel in said frequency domain; next, obtaining an execution carrier frequency offset factor, an execution phase compensation factor, and an execution gain compensation factor based on said phase error and said gain error; and finally, eliminating a phase offset of said reception signal sample of a next symbol in a time domain based on said factors, and compensating a magnitude distortion and a phase distortion on each said sub-channel in said frequency domain for said reception signal of said next symbol.
摘要翻译：一种用于OFDM系统的联合载波同步和信道均衡方法，其适用于所述正交频分复用器（OFDM）系统的接收机，包括以下步骤：首先，接收OFDM符号的接收信号样本，并获得通过在所述频域中的每个所述子信道上输出子信道信号，同时在频域中的每个子信道上产生相位误差和增益误差; 接下来，基于所述相位误差和所述增益误差获得执行载波频率偏移因子，执行相位补偿因子和执行增益补偿因子; 并且最后，基于所述因素消除在时域中的下一个符号的所述接收信号样本的相位偏移，并且在所述频域的每个所述子信道上对所述第一信号的所述接收信号的所述接收信号补偿每个所述子信道的幅度失真和相位失真下一个符号。

9. 发明授权

US07609783B2 Amplitude shift keying (ASK) demodulation circuit based on a self sample as a basis application in an organism implantation microsystem 失效
标题翻译：基于自身样本的幅移键控（ASK）解调电路作为生物体植入微系统的基础应用
公开(公告)号：US07609783B2
公开(公告)日：2009-10-27
申请号：US11464618
申请日：2006-08-15
申请人： Cihun-Siyong (Alex) Gong , Muh-Tian Shiue , Chang Yin , Su Chun-Hsien
发明人： Cihun-Siyong (Alex) Gong , Muh-Tian Shiue , Chang Yin , Su Chun-Hsien
IPC分类号： H03D1/24 , H03D1/00
CPC分类号： H04L27/06
摘要： An amplitude shift keying (ASK) demodulation circuit based on a self sample as a basis application in an organism implantation microsystem is a low-cost and high-performance ASK demodulation core, comprising a pulse shaper, a voltage scaler, a level contrastor, and a self-sampler for achievement of the demodulation core provided pretty digital features, and needs no passive resistor and capacitor, which may reduce the cost of design and prevent the problem with precision. Further, in the aspect of active point, the size of a transistor may be adjusted for variable control, and hence levels determined among modulation signals may be reduced to lower the complexity of voltage regulator in design.
摘要翻译：基于自身样本作为生物体注入微系统中的基础应用的幅度移位键控（ASK）解调电路是低成本和高性能的ASK解调核心，包括脉冲整形器，电压调节器，电平对比器和实现解调核心的自取样器提供了很好的数字特性，不需要无源电阻和电容器，这可能降低设计成本，并且精确地防止问题。此外，在有源点的方面，可以调节晶体管的尺寸用于可变控制，并且因此可以减小调制信号之间确定的电平，从而降低设计中稳压器的复杂性。

10. 发明授权

US07602844B2 On-line step-size calculation using signal power estimation and tone grouping of the frequency-domain equalizer for DMT-based transceiver 有权
标题翻译：使用基于DMT的收发器的频域均衡器的信号功率估计和音调分组的在线步长计算
公开(公告)号：US07602844B2
公开(公告)日：2009-10-13
申请号：US11293139
申请日：2005-12-05
申请人： Chih-Feng Wu , Muh-Tian Shiue , Chorng-Kuang Wang , An-Yeu Wu
发明人： Chih-Feng Wu , Muh-Tian Shiue , Chorng-Kuang Wang , An-Yeu Wu
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03159 , H04L2025/03414 , H04L2025/03687
摘要： An efficient method for calculating the step-sizes for a frequency-domain equalizer of a discrete-multitone communications system using signal power estimation and tone grouping (SPE-TG) while on-line. The SPE-TG method is used to calculate a plurality of subchannel step-sizes which are then stored in a lookup table. When on-line, the method uses signal power estimation to select step sizes for each tone, and uses these step sizes for frequency domain equalization. The SPE-TG method simplifies the calculations necessary for frequency domain equalization, thereby saving significant hardware and/or processing resources. The SPE-TG method is reliable and robust, and does not depend upon assumptions about the line, location, or channel.
摘要翻译：一种用于在线上使用信号功率估计和音调分组（SPE-TG）来计算离散多音通信系统的频域均衡器的步长的有效方法。 SPE-TG方法用于计算多个子信道步长，然后存储在查找表中。当在线时，该方法使用信号功率估计来选择每个音调的步长，并且使用这些步长来进行频域均衡。 SPE-TG方法简化了频域均衡所需的计算，从而节省了大量的硬件和/或处理资源。 SPE-TG方法是可靠和鲁棒的，不依赖于关于线路，位置或频道的假设。

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