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2. 发明授权

US09190532B2 Method of making a split gate non-volatile floating gate memory cell having a separate erase gate, and a memory cell made thereby 有权
标题翻译：制造具有单独的擦除栅极的分离栅极非易失性浮动栅极存储单元以及由此形成的存储单元的方法
公开(公告)号：US09190532B2
公开(公告)日：2015-11-17
申请号：US14240440
申请日：2012-08-08
申请人： Chunming Wang , Baowei Qiao , Zufa Zhang , Yi Zhang , Shiuh Luen Wang , Wen-Juei Lu
发明人： Chunming Wang , Baowei Qiao , Zufa Zhang , Yi Zhang , Shiuh Luen Wang , Wen-Juei Lu
IPC分类号： H01L29/788 , H01L21/28 , H01L29/423 , H01L29/66 , H01L27/115
CPC分类号： H01L29/788 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/66833
摘要： A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apart from the first region. A channel region is the first region and the second region. A word line gate is positioned over a first portion of the channel region, immediately adjacent to the first region. The word line gate is spaced apart from the channel region by a first insulating layer. A floating gate is positioned over another portion of the channel region. The floating gate has a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface. The floating gate has a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall. The second side wall and the upper surface form a sharp edge, with the second side wall greater in length than the first side wall. The upper surface slopes upward from the first side wall to the second side wall. A coupling gate is positioned over the upper surface of the floating gate and is insulated therefrom by a third insulating layer. An erase gate is positioned adjacent to the second side wall of the floating gate. The erase gate is positioned over the second region and insulated therefrom.
摘要翻译：非易失性存储单元具有具有顶表面的第一导电类型的单晶衬底。第二导电类型的第一区域沿着顶表面在衬底中。第二导电类型的第二区域沿着顶表面在与第一区域间隔开的衬底中。通道区域是第一区域和第二区域。字线门位于与第一区域紧邻的沟道区域的第一部分上方。字线栅极通过第一绝缘层与沟道区间隔开。浮动栅极位于通道区域的另一部分上。浮栅具有通过第二绝缘层与沟道区分离的下表面和与下表面相对的上表面。浮栅具有与字线门相邻但与字线门隔开的第一侧壁; 以及与第一侧壁相对的第二侧壁。第二侧壁和上表面形成锋利的边缘，第二侧壁的长度大于第一侧壁。上表面从第一侧壁向上倾斜到第二侧壁。耦合栅极位于浮动栅极的上表面上方，并通过第三绝缘层与其隔离。擦除栅极位于浮动栅极的第二侧壁附近。擦除栅极定位在第二区域上并与之绝缘。

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