专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08513728B2 Array of split gate non-volatile floating gate memory cells having improved strapping of the coupling gates 有权
标题翻译：阵列的分离栅极非易失性浮动栅极存储单元具有改进的耦合栅极的捆扎
公开(公告)号：US08513728B2
公开(公告)日：2013-08-20
申请号：US13299320
申请日：2011-11-17
申请人： Parviz Ghazavi , Hieu Van Tran , Shiuh-Luen Wang , Nhan Do , Henry A. Om'mani
发明人： Parviz Ghazavi , Hieu Van Tran , Shiuh-Luen Wang , Nhan Do , Henry A. Om'mani
IPC分类号： H01L29/788
CPC分类号： H01L27/0207 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7885
摘要： An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate.
摘要翻译：具有在行方向上延伸的具有间隔开的第一区域和在列方向上延伸的第二区域的非易失性存储器单元的阵列，其中限定在每个第二区域与其相关联的第一区域之间的通道区域。每个在行方向上延伸并定位在通道区域的第一部分上方的多个间隔开的字线门。多个间隔开的浮动栅极位于沟道区域的第二部分上方。多个间隔开的耦合栅极，每个在行方向和浮动栅极上延伸。多个间隔开的金属捆绑线，各自在行方向上延伸并且覆盖耦合门。多个间隔开的擦除栅极，每个沿行方向延伸并定位在第一区域上并且与浮栅和耦合栅极相邻。

2. 发明授权

US6020242A Effective silicide blocking 失效
标题翻译：有效的硅化物阻塞
公开(公告)号：US6020242A
公开(公告)日：2000-02-01
申请号：US926590
申请日：1997-09-04
申请人： Jiunn-Yann Tsai , Shiuh-Luen Wang , Wen-Chin Yeh
发明人： Jiunn-Yann Tsai , Shiuh-Luen Wang , Wen-Chin Yeh
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L27/10888 , H01L27/10894
摘要： A metal silicide blocking process for preventing formation of metal silicide on a first device and allowing formation of metal silicide on elements of a second device of an integrated circuit substrate is described. The process includes forming a gate electrode above the integrated circuit substrate, forming a first dielectric layer over the gate electrode and the substrate surface, forming a second dielectric layer above the first dielectric layer, etching anisotropically the second dielectric layer to form a second spacer portion adjacent to the first dielectric layer; masking the substrate surface of the first device to protect the first dielectric layer above the first device from being removed such that the substrate surface at the second device where the metal silicide is to be formed is exposed, etching the first dielectric layer to form a first spacer portion disposed between the gate electrode of the second device and the second spacer portion, the first spacer portion extends underneath the second spacer portion such that the first spacer portion is disposed between the second spacer portion and a portion of the substrate disposed beneath the second spacer portion, exposing the substrate surface of the first device, depositing a metal layer on the substrate surface and fusing metal ions from the metal layer with silicon ions from a plurality of device elements from the portion of the substrate surface where the metal silicide is to be formed to form metal silicide contact areas above the plurality of device elements.
摘要翻译：描述了用于防止在第一器件上形成金属硅化物并且允许在集成电路衬底的第二器件的元件上形成金属硅化物的金属硅化物封装工艺。该方法包括在集成电路衬底上形成栅电极，在栅电极和衬底表面上形成第一电介质层，在第一电介质层上形成第二电介质层，各向异性蚀刻第二电介质层以形成第二间隔部分邻近第一电介质层; 掩蔽第一器件的衬底表面以保护第一器件上方的第一电介质层被去除，使得将要形成金属硅化物的第二器件处的衬底表面暴露，蚀刻第一介电层以形成第一间隔部分设置在第二装置的栅电极和第二间隔部分之间，第一间隔部分在第二间隔部分下方延伸，使得第一间隔部分设置在第二间隔部分和布置在第二间隔部分下方的基底部分之间间隔部分，暴露第一器件的衬底表面，在衬底表面上沉积金属层，并将来自金属层的金属离子与来自多个器件元件的硅离子从金属硅化物的衬底表面的部分形成为在多个器件元件上方形成金属硅化物接触区域。

3. 发明授权

US09379255B2 Non-volatile memory cell having a floating gate and a coupling gate with improved coupling ratio therebetween 有权
标题翻译：具有浮动栅极和耦合栅极的非易失性存储单元，其间具有改善的耦合比
公开(公告)号：US09379255B2
公开(公告)日：2016-06-28
申请号：US14125029
申请日：2012-07-16
申请人： Chunming Wang , Baowei Qiao , Zufa Zhang , Yi Zhang , Shiuh Luen Wang , Wen-Juei Lu
发明人： Chunming Wang , Baowei Qiao , Zufa Zhang , Yi Zhang , Shiuh Luen Wang , Wen-Juei Lu
IPC分类号： H01L29/788 , H01L21/28 , H01L29/423 , H01L29/66 , H01L27/115
CPC分类号： H01L29/788 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory cell having a split gate, wherein the floating gate and the coupling/control gate have complimentary non-planar shapes. The shape may be a step shape. An array of such cells and a method of manufacturing the cells are also disclosed.
摘要翻译：一种具有分离栅极的非易失性存储单元，其中浮动栅极和耦合/控制栅极具有互补的非平面形状。形状可以是台阶形状。还公开了这种电池的阵列和制造电池的方法。

4. 发明授权

US09190532B2 Method of making a split gate non-volatile floating gate memory cell having a separate erase gate, and a memory cell made thereby 有权
标题翻译：制造具有单独的擦除栅极的分离栅极非易失性浮动栅极存储单元以及由此形成的存储单元的方法
公开(公告)号：US09190532B2
公开(公告)日：2015-11-17
申请号：US14240440
申请日：2012-08-08
申请人： Chunming Wang , Baowei Qiao , Zufa Zhang , Yi Zhang , Shiuh Luen Wang , Wen-Juei Lu
发明人： Chunming Wang , Baowei Qiao , Zufa Zhang , Yi Zhang , Shiuh Luen Wang , Wen-Juei Lu
IPC分类号： H01L29/788 , H01L21/28 , H01L29/423 , H01L29/66 , H01L27/115
CPC分类号： H01L29/788 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/66833
摘要： A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apart from the first region. A channel region is the first region and the second region. A word line gate is positioned over a first portion of the channel region, immediately adjacent to the first region. The word line gate is spaced apart from the channel region by a first insulating layer. A floating gate is positioned over another portion of the channel region. The floating gate has a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface. The floating gate has a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall. The second side wall and the upper surface form a sharp edge, with the second side wall greater in length than the first side wall. The upper surface slopes upward from the first side wall to the second side wall. A coupling gate is positioned over the upper surface of the floating gate and is insulated therefrom by a third insulating layer. An erase gate is positioned adjacent to the second side wall of the floating gate. The erase gate is positioned over the second region and insulated therefrom.
摘要翻译：非易失性存储单元具有具有顶表面的第一导电类型的单晶衬底。第二导电类型的第一区域沿着顶表面在衬底中。第二导电类型的第二区域沿着顶表面在与第一区域间隔开的衬底中。通道区域是第一区域和第二区域。字线门位于与第一区域紧邻的沟道区域的第一部分上方。字线栅极通过第一绝缘层与沟道区间隔开。浮动栅极位于通道区域的另一部分上。浮栅具有通过第二绝缘层与沟道区分离的下表面和与下表面相对的上表面。浮栅具有与字线门相邻但与字线门隔开的第一侧壁; 以及与第一侧壁相对的第二侧壁。第二侧壁和上表面形成锋利的边缘，第二侧壁的长度大于第一侧壁。上表面从第一侧壁向上倾斜到第二侧壁。耦合栅极位于浮动栅极的上表面上方，并通过第三绝缘层与其隔离。擦除栅极位于浮动栅极的第二侧壁附近。擦除栅极定位在第二区域上并与之绝缘。

5. 发明授权

US6017808A Nitrogen implanted polysilicon gate for MOSFET gate oxide hardening 失效
标题翻译：用于MOSFET栅氧化物硬化的氮注入多晶硅栅极
公开(公告)号：US6017808A
公开(公告)日：2000-01-25
申请号：US957692
申请日：1997-10-24
申请人： Shiuh-Luen Wang , Chiang-Sheng Yao , Wen-Chin Yeh
发明人： Shiuh-Luen Wang , Chiang-Sheng Yao , Wen-Chin Yeh
IPC分类号： H01L29/78 , H01L21/28 , H01L21/316 , H01L29/49 , H01L29/51 , H01L21/425 , H01L21/3205
CPC分类号： H01L21/28202 , H01L21/28044 , H01L21/28123 , H01L21/28176 , H01L29/4925 , H01L29/518
摘要： A method for hardening of gate oxide without forming low dopant concentration regions at the gate oxide-polysilicon interface is described. Polysilicon is deposited onto gate oxide followed by nitrogen implantation and annealing. At this point nitrogen concentration peaks exist at the gate oxide interfaces with the single crystal substrate and the polysilicon gate electrode. This effectively hardens the gate oxide. A third polysilicon gate electrode exists in the bulk of the polysilicon gate electrode. In the described process the region of the polysilicon layer that contains the nitrogen concentration peak is removed. An electronically active dopant may then be implanted. Alternatively, a fresh polysilicon layer may then be deposited followed by implantation of an electronically active dopant. Thus, the method of the invention avoids retardation of electronically active dopant diffusion.
摘要翻译：描述了在栅极氧化物 - 多晶硅界面处形成低掺杂浓度区域的栅极氧化物的硬化方法。将多晶硅沉积在栅极氧化物上，然后氮注入和退火。此时，在与单晶衬底和多晶硅栅电极的栅氧化物界面存在氮浓度峰。这有效地硬化了栅极氧化物。第三多晶硅栅电极存在于多晶硅栅电极的本体中。在所述工艺中，除去含有氮浓度峰的多晶硅层的区域。然后可以注入电子活性掺杂剂。或者，然后可以沉积新鲜的多晶硅层，随后注入电子活性掺杂剂。因此，本发明的方法避免了电子活性掺杂剂扩散的延迟。

6. 发明申请

US20140217489A1 A METHOD OF MAKING A SPLIT GATE NON-VOLATILE FLOATING GATE MEMORY CELL HAVING A SEPARATE ERASE GATE, AND A MEMORY CELL MADE THEREBY 有权
标题翻译：制造具有单独擦除闸门的分离栅门非挥发性闸门存储单元的方法及其存储单元
公开(公告)号：US20140217489A1
公开(公告)日：2014-08-07
申请号：US14240440
申请日：2012-08-08
申请人： Chunming Wang , Baowei Qiao , Zufa Zhang , Yi Zhang , Shiuh luen Wang , Wen-Juei Lu
发明人： Chunming Wang , Baowei Qiao , Zufa Zhang , Yi Zhang , Shiuh luen Wang , Wen-Juei Lu
IPC分类号： H01L29/788 , H01L29/66
CPC分类号： H01L29/788 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/66833
摘要： A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apart from the first region. A channel region is the first region and the second region. A word line gate is positioned over a first portion of the channel region, immediately adjacent to the first region. The word line gate is spaced apart from the channel region by a first insulating layer. A floating gate is positioned over another portion of the channel region. The floating gate has a lower surface separated from the channel region by a second insulating layer, and an upper surface opposite the lower surface. The floating gate has a first side wall adjacent to but separated from the word line gate; and a second side wall opposite the first side wall. The second side wall and the upper surface form a sharp edge, with the second side wall greater in length than the first side wall. The upper surface slopes upward from the first side wall to the second side wall. A coupling gate is positioned over the upper surface of the floating gate and is insulated therefrom by a third insulating layer. An erase gate is positioned adjacent to the second side wall of the floating gate. The erase gate is positioned over the second region and insulated therefrom.
摘要翻译：非易失性存储单元具有具有顶表面的第一导电类型的单晶衬底。第二导电类型的第一区域沿着顶表面在衬底中。第二导电类型的第二区域沿着顶表面在与第一区域间隔开的衬底中。通道区域是第一区域和第二区域。字线门位于与第一区域紧邻的沟道区域的第一部分上方。字线栅极通过第一绝缘层与沟道区间隔开。浮动栅极位于通道区域的另一部分上。浮栅具有通过第二绝缘层与沟道区分离的下表面和与下表面相对的上表面。浮栅具有与字线门相邻但与字线门隔开的第一侧壁; 以及与第一侧壁相对的第二侧壁。第二侧壁和上表面形成锋利的边缘，第二侧壁的长度大于第一侧壁。上表面从第一侧壁向上倾斜到第二侧壁。耦合栅极位于浮动栅极的上表面上方，并通过第三绝缘层与其隔离。擦除栅极位于浮动栅极的第二侧壁附近。擦除栅极定位在第二区域上并与之绝缘。

7. 发明申请

US20130126958A1 Array Of Split Gate Non-volatile Floating Gate Memory Cells Having Improved Strapping Of The Coupling Gates 有权
标题翻译：阵列的分离门非易失性浮动门存储单元改进了耦合门的捆扎
公开(公告)号：US20130126958A1
公开(公告)日：2013-05-23
申请号：US13299320
申请日：2011-11-17
申请人： Parviz Ghazavi , Hieu Van Tran , Shiuh-Luen Wang , Nhan Do , Henry A. Om'mani
发明人： Parviz Ghazavi , Hieu Van Tran , Shiuh-Luen Wang , Nhan Do , Henry A. Om'mani
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7885
摘要： An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate.
摘要翻译：具有在行方向上延伸的具有间隔开的第一区域和在列方向上延伸的第二区域的非易失性存储器单元的阵列，其中限定在每个第二区域与其相关联的第一区域之间的通道区域。每个在行方向上延伸并定位在通道区域的第一部分上方的多个间隔开的字线门。多个间隔开的浮动栅极位于沟道区域的第二部分上方。多个间隔开的耦合栅极，每个在行方向和浮动栅极上延伸。多个间隔开的金属捆绑线，各自在行方向上延伸并且覆盖耦合门。多个间隔开的擦除栅极，每个沿行方向延伸并定位在第一区域上并且与浮栅和耦合栅极相邻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式