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1. 发明授权

US08877598B2 Method of lithography process with an under isolation material layer 有权
标题翻译：具有隔离材料层的光刻工艺方法
公开(公告)号：US08877598B2
公开(公告)日：2014-11-04
申请号：US13486050
申请日：2012-06-01
申请人： Chung-Ming Wang , Yu Lun Liu , Chia-Chu Liu , Ya Hui Chang , Kuei-Shun Chen
发明人： Chung-Ming Wang , Yu Lun Liu , Chia-Chu Liu , Ya Hui Chang , Kuei-Shun Chen
IPC分类号： H01L21/336 , H01L21/4763 , H01L29/786 , H01L27/12
CPC分类号： H01L29/78606 , H01L21/02118 , H01L21/02282 , H01L21/0271 , H01L21/2652 , H01L21/31144 , H01L27/1292 , H01L29/6659
摘要： A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process.
摘要翻译：一种形成集成电路图案的方法。该方法包括在衬底上形成栅极堆叠，门堆叠的两个相邻栅堆叠被尺寸G间隔开; 在栅叠层和衬底上形成含氮层; 在所述含氮层上形成介电材料层，所述电介质材料层的厚度T大致小于G / 2; 在介电材料层上涂覆光致抗蚀剂层; 并通过光刻工艺图案化光致抗蚀剂层。

2. 发明授权

US08703392B2 Method and apparatus for developing process 有权
标题翻译：开发过程的方法和装置
公开(公告)号：US08703392B2
公开(公告)日：2014-04-22
申请号：US13602445
申请日：2012-09-04
申请人： Yu-Lun Liu , Chia-Chu Liu , Kuei-Shun Chen , Chung-Ming Wang , Ying-Hao Su
发明人： Yu-Lun Liu , Chia-Chu Liu , Kuei-Shun Chen , Chung-Ming Wang , Ying-Hao Su
IPC分类号： G03F7/26 , B05B7/00 , B05C11/00
CPC分类号： G03F7/322
摘要： The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a material layer formed thereon; depositing a photoresist layer on the material layer, the photoresist layer having a vertical dimension; exposing a region of the photoresist layer to radiation, the exposed region having a horizontal dimension, wherein a first ratio of the vertical dimension to the horizontal dimension exceeds a predetermined ratio; and developing the photoresist layer to remove the exposed region at least in part through applying a developer solution containing a first chemical and a second chemical, wherein: the first chemical is configured to dissolve the exposed region of the photoresist layer through a chemical reaction; the second chemical is configured to enhance flow of the first chemical that comes into contact with the photoresist layer; and an optimized second ratio exists between the first chemical and the second chemical.
摘要翻译：本公开涉及制造半导体器件的方法。该方法包括提供其上形成有材料层的基板; 在所述材料层上沉积光致抗蚀剂层，所述光致抗蚀剂层具有垂直尺寸; 将所述光致抗蚀剂层的区域暴露于辐射，所述暴露区域具有水平尺寸，其中所述垂直尺寸与所述水平尺寸的第一比例超过预定比率; 并且通过施加包含第一化学品和第二化学品的显影剂溶液，至少部分地显影所述光致抗蚀剂层以去除所述暴露区域，其中：所述第一化学品被配置为通过化学反应溶解所述光致抗蚀剂层的暴露区域; 第二化学品被配置为增强与光致抗蚀剂层接触的第一化学品的流动; 并且在第一化学品和第二化学品之间存在优化的第二比例。

3. 发明申请

US20140065554A1 Method and Apparatus for Developing Process 有权
标题翻译：开发过程的方法和装置
公开(公告)号：US20140065554A1
公开(公告)日：2014-03-06
申请号：US13602445
申请日：2012-09-04
申请人： Yu-Lun Liu , Chia-Chu Liu , Kuei-Shun Chen , Chung-Ming Wang , Ying-Hao Su
发明人： Yu-Lun Liu , Chia-Chu Liu , Kuei-Shun Chen , Chung-Ming Wang , Ying-Hao Su
IPC分类号： G03F7/20 , G03B27/32
CPC分类号： G03F7/322
摘要： The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a material layer formed thereon; depositing a photoresist layer on the material layer, the photoresist layer having a vertical dimension; exposing a region of the photoresist layer to radiation, the exposed region having a horizontal dimension, wherein a first ratio of the vertical dimension to the horizontal dimension exceeds a predetermined ratio; and developing the photoresist layer to remove the exposed region at least in part through applying a developer solution containing a first chemical and a second chemical, wherein: the first chemical is configured to dissolve the exposed region of the photoresist layer through a chemical reaction; the second chemical is configured to enhance flow of the first chemical that comes into contact with the photoresist layer; and an optimized second ratio exists between the first chemical and the second chemical.
摘要翻译：本公开涉及制造半导体器件的方法。该方法包括提供其上形成有材料层的基板; 在所述材料层上沉积光致抗蚀剂层，所述光致抗蚀剂层具有垂直尺寸; 将所述光致抗蚀剂层的区域暴露于辐射，所述暴露区域具有水平尺寸，其中所述垂直尺寸与所述水平尺寸的第一比例超过预定比率; 并且通过施加包含第一化学品和第二化学品的显影剂溶液，至少部分地显影所述光致抗蚀剂层以去除所述暴露区域，其中：所述第一化学品被配置为通过化学反应溶解所述光致抗蚀剂层的暴露区域; 第二化学品被配置为增强与光致抗蚀剂层接触的第一化学品的流动; 并且在第一化学品和第二化学品之间存在优化的第二比例。

4. 发明申请

US20130323898A1 METHOD OF LITHOGRAPHY PROCESS WITH AN UNDER ISOLATION MATERIAL LAYER 有权
标题翻译：具有隔离材料层的沉积工艺的方法
公开(公告)号：US20130323898A1
公开(公告)日：2013-12-05
申请号：US13486050
申请日：2012-06-01
申请人： Chung-Ming Wang , Yu Lun Liu , Chia-Chu Liu , Ya Hui Chang , Kuei-Shun Chen
发明人： Chung-Ming Wang , Yu Lun Liu , Chia-Chu Liu , Ya Hui Chang , Kuei-Shun Chen
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/78606 , H01L21/02118 , H01L21/02282 , H01L21/0271 , H01L21/2652 , H01L21/31144 , H01L27/1292 , H01L29/6659
摘要： A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process.
摘要翻译：一种形成集成电路图案的方法。该方法包括在衬底上形成栅极堆叠，门堆叠的两个相邻栅堆叠被尺寸G间隔开; 在栅叠层和衬底上形成含氮层; 在所述含氮层上形成介电材料层，所述电介质材料层的厚度T大致小于G / 2; 在介电材料层上涂覆光致抗蚀剂层; 并通过光刻工艺图案化光致抗蚀剂层。

5. 发明授权

US08765363B2 Method of forming a resist pattern with multiple post exposure baking steps 有权
标题翻译：用多次曝光后烘烤步骤形成抗蚀剂图案的方法
公开(公告)号：US08765363B2
公开(公告)日：2014-07-01
申请号：US13478559
申请日：2012-05-23
申请人： Chung-Ming Wang , Yu Lun Liu , Chia-Chu Liu , Kuei-Shun Chen
发明人： Chung-Ming Wang , Yu Lun Liu , Chia-Chu Liu , Kuei-Shun Chen
IPC分类号： G03F7/38
CPC分类号： G03F7/38 , G03F7/09 , H01L21/0274 , H01L21/76224
摘要： A method of forming a integrated circuit pattern. The method includes coating a photoresist layer on a substrate; performing a lithography exposure process to the photoresist layer; performing a multiple-step post-exposure-baking (PEB) process to the photoresist layer; and developing the photoresist layer to form a patterned photoresist layer.
摘要翻译：一种形成集成电路图案的方法。该方法包括在基底上涂覆光致抗蚀剂层; 对光致抗蚀剂层进行光刻曝光工艺; 对光致抗蚀剂层进行多步曝光后烘烤（PEB）处理; 并且显影光致抗蚀剂层以形成图案化的光致抗蚀剂层。

6. 发明申请

US20130316510A1 METHOD OF FORMING A RESIST PATTERN WITH MULTIPLE POST EXPOSURE BAKING STEPS 有权
标题翻译：形成具有多次曝光的耐力图案的方法打包步骤
公开(公告)号：US20130316510A1
公开(公告)日：2013-11-28
申请号：US13478559
申请日：2012-05-23
申请人： Chung-Ming Wang , Yu Lun Liu , Chia-Chu Liu , Kuei-Shun Chen
发明人： Chung-Ming Wang , Yu Lun Liu , Chia-Chu Liu , Kuei-Shun Chen
IPC分类号： H01L21/336 , H01L21/302 , G03F7/20
CPC分类号： G03F7/38 , G03F7/09 , H01L21/0274 , H01L21/76224
摘要： A method of forming a integrated circuit pattern. The method includes coating a photoresist layer on a substrate; performing a lithography exposure process to the photoresist layer; performing a multiple-step post-exposure-baking (PEB) process to the photoresist layer; and developing the photoresist layer to form a patterned photoresist layer.
摘要翻译：一种形成集成电路图案的方法。该方法包括在基底上涂覆光致抗蚀剂层; 对光致抗蚀剂层进行光刻曝光工艺; 对光致抗蚀剂层进行多步曝光后烘烤（PEB）处理; 并且显影光致抗蚀剂层以形成图案化的光致抗蚀剂层。

7. 发明授权

US08872339B2 Semiconductors structure with elements having different widths and methods of making the same 有权
标题翻译：具有不同宽度的元件的半导体结构及其制造方法
公开(公告)号：US08872339B2
公开(公告)日：2014-10-28
申请号：US13370828
申请日：2012-02-10
申请人： Chia-Chu Liu , Yi-Shien Mor , Kuei Shun Chen , Yu Lun Liu , Han-Hsun Chang , Shiao-Chian Yeh
发明人： Chia-Chu Liu , Yi-Shien Mor , Kuei Shun Chen , Yu Lun Liu , Han-Hsun Chang , Shiao-Chian Yeh
IPC分类号： H01L23/482 , H01L23/485 , H01L21/02
CPC分类号： H01L21/76879 , H01L21/32139 , H01L21/76802 , H01L21/76885 , H01L27/0629 , H01L2924/0002
摘要： A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.
摘要翻译：一种结构包括基底，在基底上方的第一支撑构件，在基底上方的第二支撑构件，以及在基底上方的覆盖第一支撑构件和第二支撑构件的材料层。第一支撑构件具有第一宽度，并且第二支撑构件具有第二宽度。第一支撑构件和第二支撑构件由间隙区域分开。第一宽度为第二宽度的至少10倍，间隙区域的间隙宽度为第二宽度的5至30倍。

8. 发明授权

US08932936B2 Method of forming a FinFET device 有权
标题翻译：形成FinFET器件的方法
公开(公告)号：US08932936B2
公开(公告)日：2015-01-13
申请号：US13449118
申请日：2012-04-17
申请人： Chia-Chu Liu , Kuei-Shun Chen , Chih-Hsiung Peng , Chi-Kang Chang , Chiang Mu-Chi , Sheng-Yu Chang , Hua Feng Chen , Chao-Cheng Chen , Ryan Chia-Jen Chen
发明人： Chia-Chu Liu , Kuei-Shun Chen , Chih-Hsiung Peng , Chi-Kang Chang , Chiang Mu-Chi , Sheng-Yu Chang , Hua Feng Chen , Chao-Cheng Chen , Ryan Chia-Jen Chen
IPC分类号： H01L21/00
CPC分类号： H01L21/3086 , H01L21/76224
摘要： A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings.
摘要翻译：公开了一种制造装置的方法。一种示例性的方法包括提供衬底并在衬底上形成多个鳍。该方法还包括在第一纵向方向上在基板中形成第一开口。该方法还包括在第二纵向方向上在基板中形成第二开口。第一和第二纵向是不同的。该方法还包括在第一和第二开口中沉积填充材料。

9. 发明授权

US08735994B2 Electrical-free dummy gate 有权
标题翻译：无电气虚拟门
公开(公告)号：US08735994B2
公开(公告)日：2014-05-27
申请号：US13431072
申请日：2012-03-27
申请人： Chia-Chu Liu , Kuei Shun Chen , Chiang Mu-Chi
发明人： Chia-Chu Liu , Kuei Shun Chen , Chiang Mu-Chi
IPC分类号： H01L27/088
CPC分类号： H01L21/28123 , H01L29/42372 , H01L29/78
摘要： The present disclosure provides a semiconductor device. The semiconductor device includes an electrical-free dummy gate formed over a substrate. The dummy gate has an elongate shape and is oriented along a first direction. The semiconductor device includes a first functional gate formed over the substrate. The first functional gate has an elongate shape and is oriented along the first direction. The first functional gate is separated from the dummy gate in a second direction perpendicular to the first direction. A first conductive contact is formed on the first functional gate. The semiconductor device includes a second functional gate formed over the substrate. The second functional gate has an elongate shape and is oriented along the first direction. The second functional gate is aligned with and physically separated from the dummy gate in the first direction. A second conductive contact is formed on the second functional gate.
摘要翻译：本发明提供一种半导体器件。半导体器件包括形成在衬底上的无电虚拟栅极。虚拟门具有细长形状并且沿着第一方向定向。半导体器件包括形成在衬底上的第一功能栅极。第一功能门具有细长形状并且沿着第一方向定向。第一功能门在垂直于第一方向的第二方向上与虚拟栅极分离。在第一功能栅极上形成第一导电接触。半导体器件包括形成在衬底上的第二功能栅极。第二功能门具有细长形状并且沿着第一方向定向。第二功能门与第一方向上的虚拟栅极对准并在物理上分离。在第二功能栅极上形成第二导电接触。

10. 发明申请

US20140065832A1 ENHANCED FINFET PROCESS OVERLAY MARK 有权
标题翻译：加强FINFET工艺标准
公开(公告)号：US20140065832A1
公开(公告)日：2014-03-06
申请号：US13602697
申请日：2012-09-04
申请人： Chi-Wen Hsieh , Chi-Kang Chang , Chia-Chu Liu , Meng-Wei Chen , Kuei-Shun Chen
发明人： Chi-Wen Hsieh , Chi-Kang Chang , Chia-Chu Liu , Meng-Wei Chen , Kuei-Shun Chen
IPC分类号： H01L21/308 , H01L23/544
CPC分类号： H01L23/544 , G03F7/70633 , G03F7/70683 , H01L27/0883 , H01L27/0886 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.
摘要翻译：公开了适用于制造非平面电路器件的重叠标记和形成覆盖标记的方法。示例性实施例包括接收具有有源器件区域和覆盖区域的衬底。在基板上形成一个或多个电介质层和硬掩模。图案化硬掩模以形成被配置为限定覆盖标记鳍的硬掩模层特征。间隔物形成在图案化的硬掩模层上。垫片进一步限定重叠标记鳍片和有源器件鳍片。覆盖标记鳍被切割以形成用于定义覆盖度量的参考位置的鳍线端。蚀刻电介质层和衬底以进一步限定覆盖标记鳍。

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