专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06865645B1 Program store compare handling between instruction and operand caches 有权
标题翻译：程序存储在指令和操作数缓存之间的比较处理
公开(公告)号：US06865645B1
公开(公告)日：2005-03-08
申请号：US09677527
申请日：2000-10-02
申请人： Chung-Lung Kevin Shum , Dean G. Bair , Charles F. Webb , Mark A. Check , John S. Liptay
发明人： Chung-Lung Kevin Shum , Dean G. Bair , Charles F. Webb , Mark A. Check , John S. Liptay
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3812 , G06F12/0815 , G06F12/0848
摘要： A method of supporting programs that include instructions that modify subsequent instructions in a multi-processor system with a central processing unit including an execution unit, and instruction unit and a plurality of caches including a separate instruction and operand cache.
摘要翻译：一种支持包括使用包括执行单元的中央处理单元来修改多处理器系统中的后续指令的指令的程序的方法，以及指令单元和包括单独指令和操作数高速缓存的多个高速缓存。

2. 发明授权

US06745313B2 Absolute address bits kept in branch history table 有权
标题翻译：绝对地址位保存在分支历史表中
公开(公告)号：US06745313B2
公开(公告)日：2004-06-01
申请号：US10042533
申请日：2002-01-09
申请人： John S. Liptay , Mark A. Check , Brian R. Prasky , Chung-Lung Kevin Shum
发明人： John S. Liptay , Mark A. Check , Brian R. Prasky , Chung-Lung Kevin Shum
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F12/1054 , G06F2212/6024
摘要： A method is disclosed for selecting data in a computer system having a cache memory and a branch history table, where the method includes predicting an address corresponding to the data, selecting data at the predicted address in the cache memory, translating an address corresponding to the data, comparing the translated address with the predicted address, and if they are different, re-selecting data at the translated address in the cache memory and appending the translated address to the branch history table.
摘要翻译：公开了一种用于在具有高速缓冲存储器和分支历史表的计算机系统中选择数据的方法，其中该方法包括预测对应于该数据的地址，在高速缓冲存储器中选择预测地址处的数据，数据，将转换的地址与预测地址进行比较，如果它们不同，则在高速缓冲存储器中的翻译地址处重新选择数据，并将转换的地址附加到分支历史表。

3. 发明授权

US06751708B2 Method for ensuring that a line is present in an instruction cache 有权
标题翻译：确保指令缓存中存在一行的方法
公开(公告)号：US06751708B2
公开(公告)日：2004-06-15
申请号：US10042534
申请日：2002-01-09
申请人： John S. Liptay , Mark A. Check , Mark S. Farrell , Bruce C. Giamei , Charles F. Webb
发明人： John S. Liptay , Mark A. Check , Mark S. Farrell , Bruce C. Giamei , Charles F. Webb
IPC分类号： G06F1200
CPC分类号： G06F9/3804 , G06F9/30047 , G06F9/30181 , G06F9/3838 , G06F12/0875
摘要： A method is disclosed for instructing a computing system to ensure that a line is present in an instruction cache that includes selecting a line-touch instruction, recognizing the line-touch instruction as a type of branch instruction where the branch is not taken, executing the line-touch instruction to fetch a target line from a target address into the instruction cache, and interlocking the execution of the line-touch instruction with the completion of the fetch of the target line in order to prevent execution of the instruction following the line-touch instruction until after the target line has reached the cache.
摘要翻译：公开了一种用于指示计算系统确保线路存在于指令高速缓存中的方法，所述指令高速缓存包括选择行触摸指令，将线接触指令识别为不采用分支的分支指令的类型，执行线接触指令，用于从目标地址获取目标行到指令高速缓存中，并且将行触摸指令的执行与目标行的获取完成互锁，以防止执行跟踪行指令之后的指令，触摸指令，直到目标行到达缓存。

4. 发明授权

US5625808A Read only store as part of cache store for storing frequently used millicode instructions 失效
标题翻译：只读存储作为缓存存储的一部分，用于存储常用的millicode指令
公开(公告)号：US5625808A
公开(公告)日：1997-04-29
申请号：US455820
申请日：1995-05-31
申请人： Charles F. Webb , Mark S. Farrell , Barry W. Krumm , John S. Liptay , Jennifer S. A. Navarro , Steven B. Risch , Mark A. Check
发明人： Charles F. Webb , Mark S. Farrell , Barry W. Krumm , John S. Liptay , Jennifer S. A. Navarro , Steven B. Risch , Mark A. Check
IPC分类号： G06F9/318 , G06F9/38 , G06F9/22
CPC分类号： G06F9/3802 , G06F9/3017
摘要： A read only storage (ROS) array holds a small set of relatively simple millicode instructions; those millicode instruction routines which are most commonly called on in executing common application workloads. The millicode read only store is implemented as a portion of hardware system area (HSA) storage. The cache control includes a register which contains hardware system area address corresponding to the read only store address. When an instruction fetch request is received by the cache control, the absolute address of the instruction fetch request is compared with the read only store address in the register in parallel with the normal cache directory lookup. If the instruction fetch request matches the read only store address, the fetch is made from the read only store independently of the directory lookup result.
摘要翻译：只读存储（ROS）阵列包含一小组相对简单的millicode指令; 那些在执行常见应用程序工作负载中最常调用的那些millicode指令例程。 millicode只读存储器实现为硬件系统区域（HSA）存储的一部分。高速缓存控制包括一个寄存器，该寄存器包含与只读存储地址对应的硬件系统区域地址。当缓存控制接收到指令提取请求时，将指令提取请求的绝对地址与正常缓存目录查找并行地与寄存器中的只读存储地址进行比较。如果指令提取请求与只读存储地址相匹配，则从独立于目录查找结果的只读存储进行读取。

5. 发明授权

US06671794B1 Address generation interlock detection 有权
标题翻译：地址生成互锁检测
公开(公告)号：US06671794B1
公开(公告)日：2003-12-30
申请号：US09678226
申请日：2000-10-02
申请人： Bruce C. Giamei , Mark A. Check , John S. Liptay
发明人： Bruce C. Giamei , Mark A. Check , John S. Liptay
IPC分类号： G06F938
CPC分类号： G06F9/3838 , G06F9/3824 , G06F9/3836
摘要： A method and system for detecting address generation interlock in a pipelined data processor is disclosed. The method comprises accumulating a plurality of vectors over a predefined number of processor clock cycles, with subsequent vectors corresponding to subsequent clock cycles; accumulating the status of one or more general registers in the plurality of vectors with the same bit location in each vector of the plurality of vectors corresponding to a particular general register; generating a list of pending general register updates from a logical combination of the plurality of vectors; and determining the existence of address generation interlock from the list of pending general register updates.
摘要翻译：公开了一种在流水线数据处理器中检测地址生成互锁的方法和系统。该方法包括在预定数量的处理器时钟周期上累积多个向量，后续矢量对应于随后的时钟周期; 在对应于特定通用寄存器的多个向量中的每个向量中的相同比特位置累积多个向量中的一个或多个通用寄存器的状态; 从所述多个向量的逻辑组合生成待决通用寄存器更新的列表; 并从挂起的通用寄存器更新列表中确定地址生成互锁的存在。

6. 发明申请

US20080065834A1 Method to Prevent Operand Data with No Locality from Polluting the Data Cache 审中-公开
标题翻译：防止无地点操作数据污染数据缓存的方法
公开(公告)号：US20080065834A1
公开(公告)日：2008-03-13
申请号：US11531288
申请日：2006-09-13
申请人： Mark A. Check , Jennifer A. Navarro , Charles F. Webb
发明人： Mark A. Check , Jennifer A. Navarro , Charles F. Webb
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F9/3832 , G06F12/123 , G06F2212/6028
摘要： A computer system with the means to identify based on the instruction being decoded that the operand data that this instruction will access by its nature will not have locality of access and should be installed in the cache in such a way that each successive line brought into the data cache that hits the same congruence class should be placed in the same set as to not disturb the locality of the data that resided in the cache prior to the execution of the instruction that accessed the data that will not have locality of access.
摘要翻译：一种具有根据正在被解码的指令识别的手段的计算机系统，该指令本身将访问的操作数数据将不具有访问的位置，并且应该以这样的方式安装在每个连续的行中，在同一个集合中的数据高速缓存应放置在相同的集合中，以便在执行访问不具有访问地址的数据的指令之前，不要干扰驻留在缓存中的数据的位置。

7. 发明申请

US20090259875A1 Store Clock and Store Clock Fast Instruction Execution 审中-公开
标题翻译：存储时钟和存储时钟快速指令执行
公开(公告)号：US20090259875A1
公开(公告)日：2009-10-15
申请号：US12488670
申请日：2009-06-22
申请人： Mark A. Check , Mark S. Farrell , Dan F. Greiner , James H. Mulder , Damian L. Osisek , Robert R. Rogers , Timothy J. Slegel , Ronald M. Smith, SR.
发明人： Mark A. Check , Mark S. Farrell , Dan F. Greiner , James H. Mulder , Damian L. Osisek , Robert R. Rogers , Timothy J. Slegel , Ronald M. Smith, SR.
IPC分类号： G06F1/04 , G06F9/30
CPC分类号： G06F9/30076 , G06F9/45558 , G06F9/5077 , G06F2009/45579
摘要： Two forms of TOD Clock instructions are provided, Store Clock and Store Clock Fast. Execution of the Store Clock Fast instruction may produce a time of day (TOD) result that is exactly the same as a previous TOD result, however execution of Store Clock Fast instructions while the clock is running always produce unique TOD results.
摘要翻译：提供两种形式的TOD时钟指令，快速存储时钟和存储时钟。存储时钟快速指令的执行可能产生与之前的TOD结果完全相同的时间（TOD）结果，但是在时钟运行时执行存储时钟快速指令总是产生唯一的TOD结果。

8. 发明申请

US20080082878A1 System and Method to Support Use of Bus Spare Wires in Connection Modules 失效
标题翻译：支持在连接模块中使用总线备用线的系统和方法
公开(公告)号：US20080082878A1
公开(公告)日：2008-04-03
申请号：US11531430
申请日：2006-09-13
申请人： Mark A. Check , Jonathan Y. Chen , Thomas G. Foote , Timothy J. Slegel
发明人： Mark A. Check , Jonathan Y. Chen , Thomas G. Foote , Timothy J. Slegel
IPC分类号： G01R31/28
CPC分类号： G01R31/31855 , G01R31/31717
摘要： In a computer system with multiple chips connected via a connection module with high speed elastic interface buses that support bus repair is enhanced by use of a spare net. Support is provided to ensure that the spare net can be tested in the same way that every normal bus net can be tested at all supported environments. It ensure that the system controller can find out what connections are bad and how to apply the controls to repair them for all tests and in the field for the customer.
摘要翻译：在具有通过连接模块连接的多个芯片的计算机系统中，通过使用备用网络来增强支持总线修理的高速弹性接口总线。提供支持，以确保备用网络的测试方式与每个正常总线网络在所有支持环境下都可以进行测试相同。它确保系统控制器可以找出哪些连接不好，以及如何应用控件来对所有测试进行修复，并为客户提供现场维护。

9. 发明授权

US07089408B2 Re-fetch of long operand buffered remainder after cache line invalidation in out-of-order multiprocessor system without instruction re-execution 失效
标题翻译：在无指令重新执行的无序多处理器系统中，在高速缓存行无效之后重新获取长操作数缓冲余数
公开(公告)号：US07089408B2
公开(公告)日：2006-08-08
申请号：US10435879
申请日：2003-05-12
申请人： Mark A. Check , Jennifer Navarro , Chung-Lung K. Shum
发明人： Mark A. Check , Jennifer Navarro , Chung-Lung K. Shum
IPC分类号： G06F9/34
CPC分类号： G06F9/383 , G06F9/3861
摘要： A system and method to re-fetch operand data lost for instructions with operands greater than eight bytes in length due to line invalidation due to storage update from a single or plurality of processors in a multiprocessor computer system using microprocessors that perform out of order operand fetch with respect to sequential program order in which it is not possible or desirable to kill the execution of the instruction when the storage access rules require that it appear that the operand data is accessed in program execution order.
摘要翻译：由于多处理器计算机系统中的单个或多个处理器的存储更新导致线路无效，因此使用执行无序操作数获取的微处理器，重新获取长度大于8字节的指令的操作数丢失的系统和方法关于顺序程序顺序，其中当存储访问规则要求看起来以程序执行顺序访问操作数数据时，不可能或不希望地杀死指令的执行。

10. 发明授权

US06990556B2 System and method for simultaneous access of the same doubleword in cache storage 失效
标题翻译：高速缓存存储中同一双字的同时访问的系统和方法
公开(公告)号：US06990556B2
公开(公告)日：2006-01-24
申请号：US10436221
申请日：2003-05-12
申请人： Mark A. Check , Aaron Tsai
发明人： Mark A. Check , Aaron Tsai
IPC分类号： G06F12/00
CPC分类号： G06F9/355 , G06F9/3824 , G06F9/3885 , G06F12/0851
摘要： An embodiment of the invention is a processor for providing simultaneous access to the same data for a plurality of requests. The processor includes cache storage having an address sliced directory lookup structure. A same doubleword detection unit receives a first instruction including a plurality of first instruction fields on a first pipe and a second instruction including a plurality of second instruction fields on a second pipe. The same doubleword detection unit generates a same doubleword signal in response to the first instruction fields and the second instruction fields. The cache storage reads data from a single doubleword in the cache storage and simultaneously provides the doubleword to the first pipe and the second pipe in response to the same doubleword signal.
摘要翻译：本发明的一个实施例是用于提供对多个请求的同一数据的同时访问的处理器。处理器包括具有地址分片目录查找结构的高速缓冲存储器。相同的双字检测单元在第一管道上接收包括多个第一指令字段的第一指令和在第二管道上包括多个第二指令字段的第二指令。相同的双字检测单元响应于第一指令字段和第二指令字段产生相同的双字信号。高速缓存存储器从高速缓存存储器中的单个双字读取数据，并且响应于相同的双字信号同时向第一管道和第二管道提供双字。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式