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1. 发明授权

US08723300B2 Multi-chip module power clip 有权
标题翻译：多芯片模块电源夹
公开(公告)号：US08723300B2
公开(公告)日：2014-05-13
申请号：US13584015
申请日：2012-08-13
申请人： Chung-Lin Wu , Steven Sapp , Bigildis Dosdos , Suresh Belani , Sunggeun Yoon
发明人： Chung-Lin Wu , Steven Sapp , Bigildis Dosdos , Suresh Belani , Sunggeun Yoon
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/4334 , H01L23/3107 , H01L23/49524 , H01L23/49541 , H01L23/49548 , H01L23/49562 , H01L23/49575 , H01L24/16 , H01L29/4236 , H01L29/42372 , H01L29/7813 , H01L29/7828 , H01L2224/13147 , H01L2224/16245 , H01L2224/48137 , H01L2224/48247 , H01L2924/13091 , H01L2924/15747 , H01L2924/30107 , H01L2924/00 , H01L2924/00014
摘要： The multi-chip leadless module 200 has integrated circuit (IC) 150, dual n-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.
摘要翻译：多芯片无引线模块200具有封装在树脂250中的集成电路（IC）150，双n沟道MOSFET 110，IC引线210,211,212，栅极引线213,213和源极引线217-220。IC 150 并且双n沟道MOSFET 110面朝下安装在引线上。 IC引线210,211,212由平面金属制成，并且使用倒装芯片技术分别连接到IC 150上的电极TEST，VDD和VM，以将铜柱或铜螺柱上的引线组装。

2. 发明申请

US20140042599A1 MULTI-CHIP MODULE POWER CLIP 有权
标题翻译：多芯片模块电源夹
公开(公告)号：US20140042599A1
公开(公告)日：2014-02-13
申请号：US13584015
申请日：2012-08-13
申请人： Chung-Lin Wu , Steven Sapp , Bigildis Dosdos , Suresh Belani , Sunggeun Yoon
发明人： Chung-Lin Wu , Steven Sapp , Bigildis Dosdos , Suresh Belani , Sunggeun Yoon
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/4334 , H01L23/3107 , H01L23/49524 , H01L23/49541 , H01L23/49548 , H01L23/49562 , H01L23/49575 , H01L24/16 , H01L29/4236 , H01L29/42372 , H01L29/7813 , H01L29/7828 , H01L2224/13147 , H01L2224/16245 , H01L2224/48137 , H01L2224/48247 , H01L2924/13091 , H01L2924/15747 , H01L2924/30107 , H01L2924/00 , H01L2924/00014
摘要： The multi-chip leadless module 200 has integrated circuit (IC) 150, dual re-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.
摘要翻译：多芯片无引线模块200具有集成电路（IC）150，双重信道mosfet 110，IC引线210,211,212，栅极引线213,213和封装在树脂250中的源极引线217-220。IC 150 并且双n沟道MOSFET 110面朝下安装在引线上。 IC引线210,211,212由平面金属制成，并且使用倒装芯片技术分别连接到IC 150上的电极TEST，VDD和VM，以将铜柱或铜螺柱上的引线组装。

3. 发明授权

US08487371B2 Vertical MOSFET transistor having source/drain contacts disposed on the same side and method for manufacturing the same 有权
标题翻译：具有设置在同一侧的源极/漏极触点的垂直MOSFET晶体管及其制造方法
公开(公告)号：US08487371B2
公开(公告)日：2013-07-16
申请号：US13074921
申请日：2011-03-29
申请人： Daniel M. Kinzer , Steven Sapp , Chung-Lin Wu , Oseob Jeon , Bigildis Dosdos
发明人： Daniel M. Kinzer , Steven Sapp , Chung-Lin Wu , Oseob Jeon , Bigildis Dosdos
IPC分类号： H01L29/66 , H01L23/62 , H01L27/088 , H01L21/338
CPC分类号： H01L29/7827 , H01L24/13 , H01L29/41766 , H01L29/66666 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L2224/131 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要： Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having excellent electrical performance with low drain-to-source resistance RDS(on) include using a two-metal drain contact technique. The RDS(on) is further improved by using a through-silicon-via (TSV) technique to form a drain contact or by using a copper layer closely connected to the drain drift.
摘要翻译：具有晶体管的晶体管的晶体管的晶体管的一侧制造晶圆级芯片级封装（WLCSP）器件的系统和方法仍然具有优异的电气性能，低漏极 - 源极电阻RDS（on）包括使用双金属漏极接触技术。通过使用穿硅通孔（TSV）技术来形成漏极接触或通过使用紧密连接到漏极漂移的铜层来进一步改善RDS（on）。

4. 发明申请

US20090261461A1 SEMICONDUCTOR PACKAGE WITH LEAD INTRUSIONS 审中-公开
标题翻译：半导体封装与引线插入
公开(公告)号：US20090261461A1
公开(公告)日：2009-10-22
申请号：US12104182
申请日：2008-04-16
申请人： Steven Sapp , Chung-Lin Wu , Maria Christina B. Estacio , Bigildis Dosdos , Hamza Yilmaz
发明人： Steven Sapp , Chung-Lin Wu , Maria Christina B. Estacio , Bigildis Dosdos , Hamza Yilmaz
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/49562 , H01L23/49524 , H01L23/49548 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/37147 , H01L2224/45014 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48095 , H01L2224/4813 , H01L2224/48247 , H01L2224/4846 , H01L2224/48472 , H01L2224/48599 , H01L2224/48699 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/73265 , H01L2224/84801 , H01L2224/8485 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599 , H01L2924/206
摘要： Semiconductor packages comprising a plurality of lead fingers containing a lead intrusion at the edge of the lead fingers are described. The semiconductor packages comprise an integrated circuit chip that is connected to a die pad and is electrically connected to multiple lead fingers. One or more of the lead fingers may have a lead intrusion disposed on the external exposed lower surface of the lead finger. The lead intrusion may have a height that is about ⅕ to about ½ the height of a lead finger, a width that is about ⅕ to about 1/2 the width of a lead finger, and a depth that is about ¼ to about ¾ the length of the externally exposed lower surface of a lead finger. The lead intrusion increases the area on the lead finger that contacts a bond material, such as solder, and therefore increase the strength of the joint between the semiconductor package and an external surface to which the lead finger is connected (i.e., a PCB). The lead intrusion allows out gassing during reflow of the bond material which may reduce voiding. The lead intrusion can also increase bond joint reliability by providing longer crack propagation length.
摘要翻译：描述了包括在引线的边缘处包含铅侵入的多个引线指的半导体封装。半导体封装包括连接到管芯焊盘并且电连接到多个引线指的集成电路芯片。一个或多个引导指可以具有设置在引线指的外部暴露下表面上的引线侵入。引线入侵可以具有引导指的高度的约1/5至约1/2的高度，宽度是引线指的宽度的大约1/5至大约1/2，并且深度约为1/4 到铅笔的外部暴露的下表面的长度的约3/4。引线入侵增加了引线接触诸如焊料的接合材料的引线区域，因此增加了半导体封装与引线指连接的外表面（即PCB）之间的接合强度。铅侵入允许在回流焊接材料期间放气，这可能减少空隙。铅侵入也可以通过提供更长的裂纹扩展长度来增加接合点的可靠性。

5. 发明申请

US20120248526A1 Wafer Level MOSFET Metallization 有权
标题翻译：晶圆级MOSFET金属化
公开(公告)号：US20120248526A1
公开(公告)日：2012-10-04
申请号：US13074921
申请日：2011-03-29
申请人： Daniel M. Kinzer , Steven Sapp , Chung-Lin Wu , Oseob Jeon , Bigidis Dosdos
发明人： Daniel M. Kinzer , Steven Sapp , Chung-Lin Wu , Oseob Jeon , Bigidis Dosdos
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L24/13 , H01L29/41766 , H01L29/66666 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H01L2224/131 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要： Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having excellent electrical performance with low drain-to-source resistance RDS(on) include using a two-metal drain contact technique. The RDS(on) is further improved by using a through-silicon-via (TSV) technique to form a drain contact or by using a copper layer closely connected to the drain drift.
摘要翻译：具有晶体管的晶体管的晶体管的晶体管的一侧制造晶圆级芯片级封装（WLCSP）器件的系统和方法仍然具有优异的电气性能，低漏极 - 源极电阻RDS（on）包括使用双金属漏极接触技术。通过使用穿硅通孔（TSV）技术来形成漏极接触或通过使用紧密连接到漏极漂移的铜层来进一步改善RDS（on）。

6. 发明申请

US20120144267A1 DATA READING METHOD, MEMORY STORAGE APPARATUS, AND CONTROLLER THEREOF 有权
标题翻译：数据读取方法，存储器存储器及其控制器
公开(公告)号：US20120144267A1
公开(公告)日：2012-06-07
申请号：US13037381
申请日：2011-03-01
申请人： Chih-Kang Yeh , Chien-Fu Tseng , Chung-Lin Wu
发明人： Chih-Kang Yeh , Chien-Fu Tseng , Chung-Lin Wu
IPC分类号： H03M13/05 , G06F11/10 , G06F12/00
CPC分类号： G06F11/1072 , G11C11/5642 , G11C16/28 , H03M13/6337
摘要： A data reading method for a rewritable non-volatile memory module is provided, wherein the rewritable non-volatile memory module has a plurality of physical pages. The data reading method includes grouping the physical pages into a plurality of physical page groups and configuring a corresponding threshold voltage set for each of the physical page groups. The data reading method also includes respectively reading data from the physical pages of the physical page groups by using the corresponding threshold voltage sets. The data reading method further includes when data read from one of the physical pages of one of the physical page groups cannot be corrected by using an error checking and correcting (ECC) circuit, updating the threshold voltage set corresponding to the physical page group.
摘要翻译：提供了一种用于可重写非易失性存储器模块的数据读取方法，其中可重写非易失性存储器模块具有多个物理页面。数据读取方法包括将物理页面分组成多个物理页面组并且为每个物理页面组配置相应的阈值电压集合。数据读取方法还包括通过使用相应的阈值电压组分别从物理页组的物理页面读取数据。数据读取方法还包括当通过使用错误检查和校正（ECC）电路不能校正物理页面组之一的物理页面之一读取的数据时，更新对应于物理页面组的阈值电压设置。

7. 发明授权

US08183088B2 Semiconductor die package and method for making the same 有权
标题翻译：半导体管芯封装及其制造方法
公开(公告)号：US08183088B2
公开(公告)日：2012-05-22
申请号：US12823411
申请日：2010-06-25
申请人： Oseob Jeon , Yoonhwa Choi , Boon Huan Gooi , Maria Cristina B. Estacio , Rajeev Joshi , Chung-Lin Wu , Venkat Iyer , Byoung-Ok Lee
发明人： Oseob Jeon , Yoonhwa Choi , Boon Huan Gooi , Maria Cristina B. Estacio , Rajeev Joshi , Chung-Lin Wu , Venkat Iyer , Byoung-Ok Lee
IPC分类号： H01L21/00
CPC分类号： H01L24/29 , H01L21/561 , H01L23/3121 , H01L23/4951 , H01L23/49558 , H01L23/49562 , H01L23/49575 , H01L23/49861 , H01L24/32 , H01L24/36 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/97 , H01L25/0655 , H01L2223/54406 , H01L2223/54486 , H01L2224/16 , H01L2224/291 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/293 , H01L2224/32057 , H01L2224/32225 , H01L2224/40245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45169 , H01L2224/45565 , H01L2224/456 , H01L2224/45644 , H01L2224/45669 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48237 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49113 , H01L2224/4943 , H01L2224/73204 , H01L2224/73265 , H01L2224/83192 , H01L2224/83385 , H01L2224/83801 , H01L2224/8385 , H01L2224/85013 , H01L2224/97 , H01L2924/00013 , H01L2924/00014 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/1815 , H01L2924/19043 , H01L2924/30107 , H01L2224/85 , H01L2924/00 , H01L2924/0105 , H01L2924/01082 , H01L2924/00012 , H01L2224/13111 , H01L2924/0665 , H01L2224/29099 , H01L2224/29199 , H01L2224/37099
摘要： Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.
摘要翻译：公开了半导体管芯封装。示例性半导体管芯封装包括预成型衬底。预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

8. 发明授权

US07960800B2 Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same 有权
标题翻译：具有填充弹性材料的后侧沟槽的半导体裸片，用于改善附着，使用其的封装及其制造方法
公开(公告)号：US07960800B2
公开(公告)日：2011-06-14
申请号：US12334331
申请日：2008-12-12
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
IPC分类号： H01L27/088
CPC分类号： H01L23/49513 , H01L23/49524 , H01L24/05 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L29/0657 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/291 , H01L2224/29111 , H01L2224/29139 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73255 , H01L2224/73265 , H01L2224/83856 , H01L2224/92247 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091 , H01L2924/351 , H01L2924/00 , H01L2924/0105 , H01L2924/3512 , H01L2224/45099 , H01L2224/05599 , H01L2224/37099
摘要： Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
摘要翻译：公开了具有填充有弹性导电材料的背面沟槽的半导体裸片。沟槽减小了掺入骰子的器件的导通电阻。弹性导电材料为模具的背面提供导电路径，在半导体芯片上由热循环引起的微小应力。还公开了使用骰子的包裹以及制造骰子的方法。

9. 发明申请

US20110087950A1 DATA WRITING METHOD FOR A FLASH MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME 有权
标题翻译：用于闪速存储器的数据写入方法，以及使用其的控制器和存储系统
公开(公告)号：US20110087950A1
公开(公告)日：2011-04-14
申请号：US12622084
申请日：2009-11-19
申请人： Hsiang-Hsiung Yu , Yi-Hsiang Huang , Chung-Lin Wu , Yu-Chung Shen
发明人： Hsiang-Hsiung Yu , Yi-Hsiang Huang , Chung-Lin Wu , Yu-Chung Shen
IPC分类号： G06F11/16 , G06F12/00 , G06F12/02
CPC分类号： G06F11/1072 , G06F12/0246 , G11C16/10 , G11C29/82 , G11C2029/0411
摘要： A data writing method for writing data from a host system into a flash memory chip is provided, and the flash memory chip have a plurality of physical blocks. The method includes receiving a host writing command and write data thereof, and executing the host writing command. The method also includes giving a data program command for writing the write data into one of the physical blocks to the flash memory chip, and giving a command for determining whether data stored in the physical block has any error bit. Accordingly, the method can effectively ensure the correctness of data to be written into the flash memory chip.
摘要翻译：提供了用于将数据从主机系统写入闪速存储器芯片的数据写入方法，并且闪存芯片具有多个物理块。该方法包括接收主机写入命令和写入数据，以及执行主机写入命令。该方法还包括给闪速存储器芯片提供将写入数据写入其中一个物理块的数据程序命令，并且给出用于确定存储在物理块中的数据是否具有任何错误位的命令。因此，该方法可以有效地确保要写入闪存芯片的数据的正确性。

10. 发明授权

US07845214B2 Device and method for optical nanoindentation measurement 有权
标题翻译：光学纳米压痕测量的装置和方法
公开(公告)号：US07845214B2
公开(公告)日：2010-12-07
申请号：US12230340
申请日：2008-08-28
申请人： Jiong-Shiun Hsu , Hui-Ching Lu , Chung-Lin Wu , Sheng-Jui Chen
发明人： Jiong-Shiun Hsu , Hui-Ching Lu , Chung-Lin Wu , Sheng-Jui Chen
IPC分类号： G01N3/48
CPC分类号： G01N3/405 , G01N2203/0286 , G01N2203/0641 , G01Q60/366
摘要： This invention relates to a device and method for optical nanoindentation measurement, according to which respective measurement results are obtained by having an indenter tip apply load to a fixed portion of a thin film, having an indenter tip apply load to a non-fixed portion of a thin film, and having a vibrating component transmit the dynamic properties of the vibration to the thin film. By combining the above measurement results in calculations, the Young's modulus, the Poisson's ratio, and the density of the thin film can be obtained.
摘要翻译：本发明涉及一种用于光学纳米压痕测量的装置和方法，根据该装置和方法，通过将压头施加载荷施加到薄膜的固定部分上，获得各自的测量结果，该固定部分具有压头施加载荷到非固定部分并且具有振动分量的薄膜将振动的动态特性传递给薄膜。通过在计算中结合上述测量结果，可以获得杨氏模量，泊松比和薄膜的密度。

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