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1. 发明授权

US06475894B1 Process for fabricating a floating gate of a flash memory in a self-aligned manner 有权
标题翻译：以自对准的方式制造闪存的浮动栅极的工艺
公开(公告)号：US06475894B1
公开(公告)日：2002-11-05
申请号：US10052622
申请日：2002-01-18
申请人： Chung-Lin Huang , Sheng-Tsung Chen , Chi-Hui Lin
发明人： Chung-Lin Huang , Sheng-Tsung Chen , Chi-Hui Lin
IPC分类号： H01L218247
CPC分类号： H01L27/11517 , H01L21/28273 , H01L27/115
摘要： The present invention provides a process for fabricating a floating gate of a flash memory. First, an isolation region is formed in a semiconductor substrate and the isolation region has a height higher than the substrate. A gate oxide layer and a first polysilicon layer are then formed. The first polysilicon layer is formed according to the contour of the isolation region to form a recess in the first polysilicon layer. A sacrificial insulator is filled into the recess. The first polysilicon layer is then selectively removed in a self-aligned manner using the sacrificial insulator as a hard mask to expose the isolation region. A polysilicon spacer is formed on the sidewalls of the first polysilicon layer. A first mask layer is formed on the isolation region, the sacrificial insulator in the recess is removed, and a floating gate region is defined. Then, the surfaces of the first polysilicon layer and polysilicon spacer in the floating gate region are oxidized to form a polysilicon oxide layer. Finally, the polysilicon oxide layer is used as a mask to pattern the underlying first polysilicon layer and polysilicon spacer in a self-aligned manner to form a floating gate. During the oxidation process, the polysilicon spacer of the present invention serves as a buffer layer, which is oxidized and protects the floating gate from being oxidized. Thus, the floating gate and STI overlay, and current leakage caused by insufficient overlay is prevented.
摘要翻译：本发明提供一种制造闪速存储器的浮动栅极的方法。首先，在半导体衬底中形成隔离区，并且隔离区的高度高于衬底。然后形成栅极氧化物层和第一多晶硅层。第一多晶硅层根据隔离区域的轮廓形成，以在第一多晶硅层中形成凹陷。牺牲绝缘体填充到凹部中。然后使用牺牲绝缘体作为硬掩模以自对准方式选择性地去除第一多晶硅层以暴露隔离区域。在第一多晶硅层的侧壁上形成多晶硅间隔物。在隔离区域上形成第一掩模层，去除凹槽中的牺牲绝缘体，并且限定浮栅区域。然后，浮置栅极区域中的第一多晶硅层和多晶硅间隔物的表面被氧化以形成多晶硅氧化物层。最后，使用多晶硅氧化物层作为掩模，以自对准的方式对下面的第一多晶硅层和多晶硅间隔物进行图案化以形成浮栅。在氧化过程中，本发明的多晶硅间隔物用作缓冲层，其被氧化并保护浮栅不被氧化。因此，防止浮动栅极和STI覆盖，以及由覆盖不足引起的电流泄漏。

2. 发明授权

US06921694B2 Method for fabricating floating gate 有权
标题翻译：浮栅制造方法
公开(公告)号：US06921694B2
公开(公告)日：2005-07-26
申请号：US10442308
申请日：2003-05-19
申请人： Ying-Cheng Chuang , Chung-Lin Huang , Chi-Hui Lin
发明人： Ying-Cheng Chuang , Chung-Lin Huang , Chi-Hui Lin
IPC分类号： H01L21/28 , H01L29/423 , H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273
摘要： A method for fabricating a floating gate with multiple tips. A semiconductor substrate is provided, on which an insulating layer and a patterned hard mask layer are sequentially formed. The patterned hard mask layer has an opening to expose the surface of the semiconductor substrate. A conducting layer is conformally formed on the patterned hard mask layer, and the opening is filled with the conducting layer. The conducting layer is planarized to expose the surface of the patterned hard mask layer. The conducting layer is thermally oxidized to form an oxide layer, and the patterned hard mask layer is removed.
摘要翻译：一种用于制造具有多个尖端的浮动栅极的方法。提供半导体衬底，其上依次形成绝缘层和图案化的硬掩模层。图案化的硬掩模层具有露出半导体衬底的表面的开口。在图案化的硬掩模层上共形形成导电层，并且该开口填充有导电层。导电层被平坦化以暴露图案化的硬掩模层的表面。导电层被热氧化以形成氧化物层，去除图案化的硬掩模层。

3. 发明授权

US06768164B2 Stacked gate flash memory device and method of fabricating the same 有权
公开(公告)号：US06768164B2
公开(公告)日：2004-07-27
申请号：US10725052
申请日：2003-12-01
申请人： Chi-Hui Lin , Chung-Lin Huang
发明人： Chi-Hui Lin , Chung-Lin Huang
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42336 , H01L29/66825 , H01L29/7883
摘要： A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate and source and drain regions are formed in the same substrate side of the adjacent isolation trenches. Thus, the stacked gate flash memory device of the invention can achieve high integration of memory cells.

4. 发明授权

US06451654B1 Process for fabricating self-aligned split gate flash memory 有权
标题翻译：制造自对准分裂门闪存的工艺
公开(公告)号：US06451654B1
公开(公告)日：2002-09-17
申请号：US10029429
申请日：2001-12-18
申请人： Chi-Hui Lin , Chung-Lin Huang , Yung-Meng Huang
发明人： Chi-Hui Lin , Chung-Lin Huang , Yung-Meng Huang
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention provides a process for fabricating a self-aligned split gate flash memory. First, a patterned gate oxide layer, a first patterned polysilicon layer, and a first patterned mask layer are successively formed on a semiconductor substrate, and a first insulating spacer is formed on their sidewalls. Then, shallow trench isolation (STI) is formed in the substrate using the first patterned mask layer and the first insulating spacer as a mask. Then, the first patterned mask layer and a part of the first insulating spacer are removed to expose the first patterned polysilicon layer. A floating gate region is defined on the first patterned polysilicon layer, and the surface of the first polysilicon layer in the floating gate region is selectively oxidized to form polysilicon oxide layer. Then, the polysilicon oxide layer is used as a mask to remove the underlying first polysilicon layer in a self-aligned manner to form a floating gate. Finally, an intergate insulating layer and a second patterned polysilicon layer as a control gate are succesively formed on the polysilicon oxide layer. The present invention forms a floating gate in a self-aligned manner, which can decreases critical dimension. When an oxidation process is conducted to form the above polysilicon oxide layer, the nitride liner layer and the insulating spacer formed in the trench protect the sides of floating gate from oxygen invasion. This prevents the line width of floating gate from size reduction. Current leakage is also be avoided.
摘要翻译：本发明提供一种用于制造自对准分离栅闪存的方法。首先，在半导体衬底上依次形成图案化栅极氧化物层，第一图案化多晶硅层和第一图案化掩模层，并且在其侧壁上形成第一绝缘间隔物。然后，使用第一图案化掩模层和第一绝缘间隔物作为掩模在衬底中形成浅沟槽隔离（STI）。然后，去除第一图案化掩模层和第一绝缘间隔物的一部分以露出第一图案化多晶硅层。在第一图案化多晶硅层上限定浮栅区域，并且浮栅区域中的第一多晶硅层的表面被选择性地氧化以形成多晶硅氧化物层。然后，将多晶硅氧化物层用作掩模，以自对准的方式去除下面的第一多晶硅层以形成浮动栅极。最后，在多晶硅氧化物层上连续地形成作为控制栅极的栅极绝缘层和第二图案化多晶硅层。本发明以自对准的方式形成浮动栅极，这可以降低临界尺寸。当进行氧化处理以形成上述多晶硅氧化物层时，形成在沟槽中的氮化物衬垫层和绝缘衬垫保护浮动栅极的侧面免受氧气侵入。这样可以防止浮动栅极的线宽缩小。电流泄漏也被避免。

5. 发明申请

US20070063260A1 Floating gate and fabricating method thereof 有权
标题翻译：浮栅及其制造方法
公开(公告)号：US20070063260A1
公开(公告)日：2007-03-22
申请号：US11603771
申请日：2006-11-22
申请人： Ying-Cheng Chuang , Chung-Lin Huang , Chi-Hui Lin
发明人： Ying-Cheng Chuang , Chung-Lin Huang , Chi-Hui Lin
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42324 , H01L29/7881
摘要： A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.
摘要翻译：浮栅及其制造方法。提供了半导体衬底，其上依次形成有氧化物层，第一导电层和具有开口的图案化硬掩模层。间隔件形成在开口的侧壁上。在硬掩模层上形成第二导电层。将第二导电层平坦化以暴露图案化硬掩模层的表面。第二导电层的表面被氧化形成氧化物层。图案化的硬掩模层和氧化物层以及图案化的硬掩模层下面的第一导电层被去除。

6. 发明授权

US06900112B2 Process for forming shallow trench isolation region with corner protection layer 有权
标题翻译：用角保护层形成浅沟槽隔离区的工艺
公开(公告)号：US06900112B2
公开(公告)日：2005-05-31
申请号：US10426348
申请日：2003-04-30
申请人： Chi-Hui Lin , Chung-Lin Huang
发明人： Chi-Hui Lin , Chung-Lin Huang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A process for forming shallow trench isolation region with corner protection layer. A protection layer is formed within the opening that defines the isolation trench as part of the etching mask such that the etching rate of the protection layer is less than the mask layer and the pad insulating layer to the etchant used to remove the mask layer and pad insulating layer. The protection layer is partially removed and left adjacent to the shallow trench isolation region as a corner protection layer after removing the mask layer and pad insulating layer. Thus, the indentation next to the corner of the isolation region is avoided.
摘要翻译：用于形成具有角保护层的浅沟槽隔离区的工艺。在开口内形成保护层，其将隔离沟槽定义为蚀刻掩模的一部分，使得保护层的蚀刻速率小于用于去除掩模层和焊盘的掩模层和蚀刻剂的焊盘绝缘层绝缘层。在去除掩模层和焊盘绝缘层之后，保护层被部分地去除并且与作为转角保护层的浅沟槽隔离区相邻。因此，避免了隔离区域的拐角附近的压痕。

7. 发明申请

US20050101090A1 Floating gate and fabrication method therefor 审中-公开
标题翻译：浮门及其制造方法
公开(公告)号：US20050101090A1
公开(公告)日：2005-05-12
申请号：US11014483
申请日：2004-12-15
申请人： Ying-Cheng Chuang , Chung-Lin Huang , Chi-Hui Lin
发明人： Ying-Cheng Chuang , Chung-Lin Huang , Chi-Hui Lin
IPC分类号： H01L21/28 , H01L29/423 , H01L21/336
CPC分类号： H01L29/42324 , H01L29/40114
摘要： A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.
摘要翻译：具有多个尖端的浮动栅极及其制造方法。提供半导体衬底，在其上形成图案化的硬掩模层，其中图案化的硬掩模层具有开口。在开口的底部形成具有第一预定厚度的栅介质层和第一导电层。间隔件形成在开口的侧壁上。导电间隔件形成在间隔件的侧壁上。第一导电层被蚀刻到第二预定厚度。由第一导电层和导电间隔物提供多尖端浮栅。在开口中形成保护层。蚀刻图案化的硬掩模层，栅介质层，保护层的一部分和第一间隔物的一部分，以露出第一导电层的表面。

8. 发明授权

US06800526B2 Method for manufacturing a self-aligned split-gate flash memory cell 有权
标题翻译：用于制造自对准分裂闸闪存单元的方法
公开(公告)号：US06800526B2
公开(公告)日：2004-10-05
申请号：US10302865
申请日：2002-11-25
申请人： Chi-Hui Lin , Chung-Lin Huang , Cheng-Chih Huang
发明人： Chi-Hui Lin , Chung-Lin Huang , Cheng-Chih Huang
IPC分类号： H01L21336
CPC分类号： H01L29/42332 , H01L21/28273
摘要： A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.
摘要翻译：一种分离栅闪存单元的制造方法，包括以下步骤：在半导体衬底上形成有源区; 在半导体衬底上形成缓冲层; 在缓冲层上形成第一介电层; 去除所述第一电介质层的一部分; 定义一个开口去除开口内的缓冲层; 形成栅绝缘层和浮栅; 在所述半导体衬底中形成源区; 在开口上沉积共形的第二介电层; 去除第一介电层和浮栅之外的缓冲层; 并形成氧化物层和控制栅极。

9. 发明授权

US06673676B2 Method of fabricating a flash memory cell 有权
标题翻译：制造闪存单元的方法
公开(公告)号：US06673676B2
公开(公告)日：2004-01-06
申请号：US10229529
申请日：2002-08-27
申请人： Chi-Hui Lin , Chung-Lin Huang , Cheng-Chih Huang
发明人： Chi-Hui Lin , Chung-Lin Huang , Cheng-Chih Huang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of fabricating a flash memory cell. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer on the first gate insulating layer; forming a floating gate insulating layer; forming a source region by implanting impurity ions into the substrate; forming a second insulating layer; forming a floating gate region; forming a third insulating; forming a second conductive layer on the third insulating layer; forming a fourth insulating layer on the second conductive layer; forming a floating gate region; forming a second conductive layer on the third insulating layer; forming first sidewall spacers; forming control gates and a tunneling oxide; forming second sidewall spacers; and forming a drain region on the substrate.
摘要翻译：一种制造闪存单元的方法。该方法包括提供半导体衬底的步骤; 形成第一栅极绝缘层; 在所述第一栅极绝缘层上形成第一导电层; 形成浮栅绝缘层; 通过将杂质离子注入衬底来形成源区; 形成第二绝缘层; 形成浮栅区域; 形成第三绝缘层; 在所述第三绝缘层上形成第二导电层; 在所述第二导电层上形成第四绝缘层; 形成浮栅区域; 在所述第三绝缘层上形成第二导电层; 形成第一侧壁间隔物; 形成控制栅极和隧道氧化物; 形成第二侧壁间隔物; 以及在所述衬底上形成漏区。

10. 发明授权

US06770520B2 Floating gate and method of fabricating the same 有权
标题翻译：浮门及其制造方法
公开(公告)号：US06770520B2
公开(公告)日：2004-08-03
申请号：US10436800
申请日：2003-05-13
申请人： Ying-Cheng Chuang , Chung-Lin Huang , Chi-Hui Lin
发明人： Ying-Cheng Chuang , Chung-Lin Huang , Chi-Hui Lin
IPC分类号： H01L21337
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which a gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed. The surface of the conducting layer is covered by the patterned hard mask layer to form a gate. The conducting layer is etched to a predetermined depth to form an indentation using the patterned hard mask layer as a mask. The conducting layer is oxidized to form an oxide layer on the surface of the conducting layer. The oxide layer and the conducting layer are etched to form multiple tips using the patterned hard mask layer as a mask.
摘要翻译：浮栅及其制造方法。提供半导体衬底，其上依次形成栅介电层，导电层和图案化的硬掩模层。导电层的表面被图案化的硬掩模层覆盖以形成栅极。使用图案化的硬掩模层作为掩模，将导电层蚀刻到预定深度以形成凹陷。导电层被氧化以在导电层的表面上形成氧化物层。使用图案化的硬掩模层作为掩模，蚀刻氧化物层和导电层以形成多个尖端。

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