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1. 发明授权

US08542532B2 Memory access method and flash memory using the same 有权
标题翻译：内存访问方法和闪存使用相同
公开(公告)号：US08542532B2
公开(公告)日：2013-09-24
申请号：US13298443
申请日：2011-11-17
申请人： Chung-Kuang Chen , Shuo-Nan Hung , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/32
摘要： A memory access method is applied in a memory controller for accessing an NAND memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes the following steps. A stream bias signal and a selected word line signal are respectively provided on a selected stream and on a selected cell of the selected stream, and the rest of memory cells are turned on as pass transistors, in the setup phase. A discharge path is provided to eliminate coupling charge presented on unselected streams, in the setup phase. Then, the string select signal is enabled to have the selected stream connected to a sense unit via a metal bit line and according read the selected cell in a voltage sensing scheme, in a read phase, which does not overlap with the setup phase.
摘要翻译：存储器访问方法应用于存储器控制器中，用于访问NAND存储器阵列，包括通过字符串选择信号全局控制的多个相应的选择开关。存储器访问方法包括以下步骤。在所选择的流和所选择的流的所选择的单元上分别提供流偏置信号和选择的字线信号，并且在设置阶段中，剩余的存储器单元作为传输晶体管被导通。提供放电路径以消除在设置阶段中呈现在未选择的流上的耦合电荷。然后，串选择信号被使能以使所选择的流通过金属位线连接到感测单元，并且在读取阶段以读取阶段读取所选择的单元，其不与设置阶段重叠。

2. 发明申请

US20130128670A1 MEMORY ACCESS METHOD AND FLASH MEMORY USING THE SAME 有权
标题翻译：存储器访问方法和使用该存储器的闪存存储器
公开(公告)号：US20130128670A1
公开(公告)日：2013-05-23
申请号：US13298443
申请日：2011-11-17
申请人： Chung-Kuang Chen , Shuo-Nan Hung , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Shuo-Nan Hung , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/32
摘要： A memory access method is applied in a memory controller for accessing an NAND memory array, including a number of respective select switches globally controlled with a string select signal. The memory access method includes the following steps. A stream bias signal and a selected word line signal are respectively provided on a selected stream and on a selected cell of the selected stream, and the rest of memory cells are turned on as pass transistors, in the setup phase. A discharge path is provided to eliminate coupling charge presented on unselected streams, in the setup phase. Then, the string select signal is enabled to have the selected stream connected to a sense unit via a metal bit line and according read the selected cell in a voltage sensing scheme, in a read phase, which does not overlap with the setup phase.
摘要翻译：存储器访问方法应用于存储器控制器中，用于访问NAND存储器阵列，包括通过字符串选择信号全局控制的多个相应的选择开关。存储器访问方法包括以下步骤。在所选择的流和所选择的流的所选择的单元上分别提供流偏置信号和选择的字线信号，并且在设置阶段中，剩余的存储器单元作为传输晶体管被导通。提供放电路径以消除在设置阶段中呈现在未选择的流上的耦合电荷。然后，串选择信号被使能以使所选择的流通过金属位线连接到感测单元，并且在读取阶段以读取阶段读取所选择的单元，其不与设置阶段重叠。

3. 发明授权

US09449666B2 Local word line driver 有权
标题翻译：本地字线驱动
公开(公告)号：US09449666B2
公开(公告)日：2016-09-20
申请号：US13713829
申请日：2012-12-13
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C8/08 , G11C7/12
CPC分类号： G11C8/08 , G11C7/12
摘要： A memory circuit with a word line driver and control circuitry is disclosed. The plurality of word line drivers are coupled to a plurality of word lines. Word line drivers include a CMOS inverter, which can have an input and an output, and a p-type transistor and an n-type transistor. The output of the CMOS inverter is coupled to one of the plurality of word lines. The control circuitry has multiple modes, including at least a first mode to discharge a particular word line of the plurality of word lines via a first discharge path such as at least a first transistor type of the CMOS inverter; and a second mode to discharge the particular word line of the plurality of word lines via a second discharge path such as at least the a second transistor type of the CMOS inverter.
摘要翻译：公开了具有字线驱动器和控制电路的存储器电路。多个字线驱动器耦合到多个字线。字线驱动器包括可以具有输入和输出的CMOS反相器，以及p型晶体管和n型晶体管。 CMOS反相器的输出耦合到多个字线之一。控制电路具有多种模式，包括至少第一模式，以经由诸如至少第一晶体管类型的CMOS反相器的第一放电路径放电多个字线的特定字线; 以及第二模式，用于经由诸如至少第二晶体管类型的CMOS反相器的第二放电路径放电多个字线的特定字线。

4. 发明申请

US20130215687A1 Method and Apparatus for Dynamic Sensing Window in Memory 有权
标题翻译：存储器中动态感应窗口的方法和装置
公开(公告)号：US20130215687A1
公开(公告)日：2013-08-22
申请号：US13402327
申请日：2012-02-22
申请人： Han-Sung Chen , Chung-Kuang Chen , Chun-Hsiung Hung
发明人： Han-Sung Chen , Chung-Kuang Chen , Chun-Hsiung Hung
IPC分类号： G11C7/14 , G11C7/00
CPC分类号： G11C11/5642 , G11C16/00 , G11C29/021 , G11C29/028 , G11C29/42 , G11C2211/5634
摘要： A memory array is characterized by a threshold definition, which includes threshold voltage ranges representing data values stored by a part of the memory array, and a set of sense windows separating the threshold voltage ranges. The threshold definition is varied, responsive to at least one of program operations and erase operations. Such operations change a distribution of the data values stored in the memory group.
摘要翻译：存储器阵列的特征在于阈值定义，其包括表示由存储器阵列的一部分存储的数据值的阈值电压范围，以及分离阈值电压范围的一组感测窗口。响应于程序操作和擦除操作中的至少一个，阈值定义是变化的。这样的操作改变存储在存储器组中的数据值的分布。

5. 发明申请

US20130058181A1 MEMORY WITH TEMPERATURE COMPENSATION 有权
标题翻译：存储温度补偿
公开(公告)号：US20130058181A1
公开(公告)日：2013-03-07
申请号：US13227249
申请日：2011-09-07
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C7/14 , G11C11/5642 , G11C2211/5634
摘要： A memory element in which the temperature coefficient of a memory cell substantially matches the temperature coefficient of a reference cell and tuning either the temperature coefficient of a memory cell to substantially match the temperature coefficient of the reference cell provides for improved precision of sensing or reading memory element states, particularly so as to minimize the affect of temperature variations on reading and sensing states.
摘要翻译：一种存储元件，其中存储单元的温度系数基本上与参考单元的温度系数相匹配，并且调节存储单元的温度系数以与参考单元的温度系数基本一致，提供了读取或读取存储器的精度提高特别是为了最小化温度变化对读取和感测状态的影响。

6. 发明申请

US20120224443A1 SENSE AMPLIFIER WITH SHIELDING CIRCUIT 有权
标题翻译： SENSE放大器与屏蔽电路
公开(公告)号：US20120224443A1
公开(公告)日：2012-09-06
申请号：US13474270
申请日：2012-05-17
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C7/06 , H03F3/45 , H03F3/04
CPC分类号： G11C7/062 , G11C7/02
摘要： A sense amplifier includes a first transistor, a second transistor, an output circuit, and a shielding circuit. The first transistor has a gate bias established by a cell current, and the second transistor has a gate bias established by a reference current. The output circuit is coupled to the first and the second transistor. The shielding circuit is located between the second transistor and the output circuit.
摘要翻译：读出放大器包括第一晶体管，第二晶体管，输出电路和屏蔽电路。第一晶体管具有由单元电流建立的栅极偏置，并且第二晶体管具有由参考电流建立的栅极偏置。输出电路耦合到第一和第二晶体管。屏蔽电路位于第二晶体管和输出电路之间。

7. 发明授权

US08245074B2 Clock integrated circuit 有权
标题翻译：时钟集成电路
公开(公告)号：US08245074B2
公开(公告)日：2012-08-14
申请号：US12631693
申请日：2009-12-04
申请人： Chung-Kuang Chen , Chun-Hsiung Hung , Han-Sung Chen
发明人： Chung-Kuang Chen , Chun-Hsiung Hung , Han-Sung Chen
IPC分类号： G06F1/12 , G06F1/00 , G06F1/04 , G06F11/00 , H03B5/32
CPC分类号： G06F1/04 , H03K19/00384
摘要： The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.
摘要翻译：集成电路的时钟电路具有诸如温度，接地噪声和功率噪声的变化。改进的时钟集成电路的各个方面解决了温度，地面噪声和功率噪声中的一个或多个变化。

8. 发明申请

US20120019232A1 Current Source with Tunable Voltage-Current Coefficient 有权
标题翻译：具有可调谐电压 - 电流系数的电流源
公开(公告)号：US20120019232A1
公开(公告)日：2012-01-26
申请号：US12840943
申请日：2010-07-21
申请人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chung-Kuang Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G05F3/02
CPC分类号： G05F1/561
摘要： A current source providing an output current with a fixed current range includes a bias circuit, a resistor, a current mirror, and a controller. The bias circuit provides a first voltage weighted with a first tunable coefficient and a second voltage weighted with a second tunable coefficient. The resistor has a tunable resistance for determining a bias current according to a voltage difference between the first and the second voltages and the tunable resistance. The current mirror generates the output current according to the bias current. The controller adjusts the tunable resistance and one of the first and the second tunable coefficients to achieve a voltage-current coefficient with different values, while the bias current and the output current are kept within a fixed current range.
摘要翻译：提供具有固定电流范围的输出电流的电流源包括偏置电路，电阻器，电流镜和控制器。偏置电路提供用第一可调系数和第二可调系数加权的第二电压加权的第一电压。电阻器具有根据第一和第二电压之间的电压差以及可调谐电阻来确定偏置电流的可调电阻。电流镜根据偏置电流产生输出电流。控制器调节可调谐电阻和第一和第二可调谐系数之一，以实现具有不同值的电压 - 电流系数，而偏置电流和输出电流保持在固定电流范围内。

9. 发明授权

US08064263B2 Current sink system for source-side sensing 有权
标题翻译：电流源系统用于源侧感测
公开(公告)号：US08064263B2
公开(公告)日：2011-11-22
申请号：US12576466
申请日：2009-10-09
申请人： Chun-Hsiung Hung , Han-Sung Chen , Chung-Kuang Chen
发明人： Chun-Hsiung Hung , Han-Sung Chen , Chung-Kuang Chen
IPC分类号： G11C13/06
CPC分类号： G11C7/067 , G11C7/062 , G11C7/14 , G11C16/28 , G11C2207/063
摘要： Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell.
摘要翻译：基于来自存储单元的源极端子的读取电流与从读出电流抽取的吸收电流之间的电流差，确定存储单元中存储的源极侧感测技术。吸收电流响应于由参考电流源（例如参考单元）提供的参考电流的大小来绘制。

10. 发明授权

US07990990B2 Circuit and method for transmitting data stream 有权
标题翻译：用于传输数据流的电路和方法
公开(公告)号：US07990990B2
公开(公告)日：2011-08-02
申请号：US11953940
申请日：2007-12-11
申请人： Chung-Kuang Chen , Chun-Hsiung Hung , Yi-Te Shih
发明人： Chung-Kuang Chen , Chun-Hsiung Hung , Yi-Te Shih
IPC分类号： H04L12/28
CPC分类号： G11C16/26 , G11C7/1012 , G11C7/1027 , G11C2207/002
摘要： A circuit including a first data selection circuit and a second data selection circuit for transmitting a data stream is provided. The first data selection circuit having first controllable channels turns on a first operating channel being one of the first controllable channels in an odd-numbered period and turns off the first controllable channels in an even-numbered period adjacent to the odd-numbered period for transmitting a first bit datum of the data stream. The second data selection circuit having second controllable channels turns off the second controllable channels in the odd-numbered period and turns on a second operating channel being one of the second controllable channels in the even-numbered period for transmitting a second bit datum of the data stream.
摘要翻译：提供一种包括第一数据选择电路和用于发送数据流的第二数据选择电路的电路。具有第一可控通道的第一数据选择电路在奇数周期中导通作为第一可控通道之一的第一操作信道，并在偶数周期中关闭与奇数周期相邻的第一可控通道，用于发送数据流的第一个位数据。具有第二可控通道的第二数据选择电路在奇数周期中关闭第二可控通道，并且在偶数周期中接通作为第二可控通道之一的第二操作通道，用于发送数据的第二位数据流。

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