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1. 发明授权

US5888861A Method of manufacturing a BiCMOS integrated circuit fully integrated within a CMOS process flow 失效
标题翻译：制造完全集成在CMOS工艺流程中的BiCMOS集成电路的方法
公开(公告)号：US5888861A
公开(公告)日：1999-03-30
申请号：US870474
申请日：1997-06-06
申请人： Chung-Jen Chien , Jeong Y. Choi , Chuen-Der Lien
发明人： Chung-Jen Chien , Jeong Y. Choi , Chuen-Der Lien
IPC分类号： H01L21/8249 , H01L21/8238
CPC分类号： H01L21/8249
摘要： A process for manufacturing a BiCMOS integrated circuit is implemented by adapting the masking and doping steps used in forming CMOS devices. Thus simultaneous formation of both CMOS and bipolar device structures eliminates the need for any additional masking or process steps to form bipolar device structures. Collector regions 20 of NPN transistors are formed simultaneously with N-wells 18. Collector regions of PNP transistors, if required, are formed simultaneously with P-wells 16. Base regions 24 of the bipolar transistors are formed using threshold voltage implant steps and/or lightly doped drain implant steps of PMOS transistors. Emitter regions 59 are formed, when using a single polysilicon CMOS process, simultaneously with the CMOS gates 72, 74. When employing a double polysilicon CMOS process, the emitter regions 59 are formed concurrently with the second polysilicon layer interconnect structure and/or source/drain regions 50,52 of NMOS transistors. For single polysilicon CMOS process, the buried layer regions 66 are formed during buried contact formation.
摘要翻译： BiCMOS集成电路的制造工艺通过适应用于形成CMOS器件的掩模和掺杂步骤来实现。因此同时形成CMOS和双极器件结构消除了对形成双极器件结构的任何附加掩模或工艺步骤的需要。 NPN晶体管的集电极区域20与N阱18同时形成。如果需要，PNP晶体管的集电极区域与P阱16同时形成。双极晶体管的基极区域24使用阈值电压注入步骤和/或 PMOS晶体管的轻掺杂漏极注入步骤。当使用单个多晶硅CMOS工艺时，发射极区59与CMOS栅极72,74同时形成。当采用双重多晶硅CMOS工艺时，发射极区59与第二多晶硅层互连结构和/或源/ NMOS晶体管的漏极区域50,52。对于单多晶硅CMOS工艺，在掩埋接触形成期间形成掩埋层区域66。

2. 发明授权

US06127710A CMOS structure having a gate without spacers 失效
标题翻译： CMOS结构具有不带间隔物的栅极
公开(公告)号：US06127710A
公开(公告)日：2000-10-03
申请号：US900811
申请日：1997-07-25
申请人： Jeong Yeol Choi , Chung-Jen Chien , Chung-Chyung Han , Chuen-Der Lien
发明人： Jeong Yeol Choi , Chung-Jen Chien , Chung-Chyung Han , Chuen-Der Lien
IPC分类号： H01L21/762 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823864 , H01L21/76202 , H01L21/823814 , H01L21/823871 , H01L21/823892
摘要： A CMOS Structure is disclosed wherein two adjacent transistors of opposite conductivity each have a gate above their respective channel regions. Spacers are absent from the gate of one of the transistors. The structure is also characterized by lightly doped regions.
摘要翻译：公开了CMOS结构，其中具有相反导电性的两个相邻的晶体管每个在它们各自的沟道区上方具有栅极。其中一个晶体管的栅极不存在间隔。该结构的特征还在于轻掺杂区域。

3. 发明授权

US5793088A Structure for controlling threshold voltage of MOSFET 失效
标题翻译：控制MOSFET阈值电压的结构
公开(公告)号：US5793088A
公开(公告)日：1998-08-11
申请号：US664440
申请日：1996-06-18
申请人： Jeong Yeol Choi , Chung-Jen Chien , Chung Chyung Han , Chuen-Der Lien
发明人： Jeong Yeol Choi , Chung-Jen Chien , Chung Chyung Han , Chuen-Der Lien
IPC分类号： H01L21/266 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6659 , H01L21/266 , H01L21/8238 , H01L27/0928 , H01L29/1033 , H01L29/1045 , H01L29/1083 , H01L29/6656
摘要： A method and structure for controlling the threshold voltage of a MOSFET is provided. The method compensates for the edge effect associated with prior art halo implants by providing an edge threshold voltage implant (the VT implant) which passes impurities through dielectric spacers, through the underlying source/drain regions and into the edges of the halo regions which lie in the channel. The VT implant reduces junction capacitance and does not degrade punchthrough voltage.
摘要翻译：提供了用于控制MOSFET的阈值电压的方法和结构。该方法通过提供边缘阈值电压注入（VT注入）来补偿与现有技术的光晕植入物相关的边缘效应，该边缘阈值电压注入（VT注入）使杂质通过电介质间隔物穿过下面的源极/漏极区域并进入位于这个频道。 VT注入降低结电容，不会降低穿通电压。

4. 发明授权

US5750424A Method for fabricating a CMOS device 失效
标题翻译： CMOS器件制造方法
公开(公告)号：US5750424A
公开(公告)日：1998-05-12
申请号：US764662
申请日：1996-12-10
申请人： Jeong Yeol Choi , Chung-Jen Chien , Chung-Chyung Han , Chuen-Der Lien
发明人： Jeong Yeol Choi , Chung-Jen Chien , Chung-Chyung Han , Chuen-Der Lien
IPC分类号： H01L21/762 , H01L21/8238
CPC分类号： H01L21/823864 , H01L21/76202 , H01L21/823814 , H01L21/823871 , H01L21/823892
摘要： A process for fabricating a CMOS structure using a single masking step to define lightly-doped source and drain regions for both N- and P-channel devices. The process forms disposable spacers adjacent to gate structures and at least one retrograde well. Retrograde wells are formed using one or more charged ions at different energy levels. In addition, heavily-doped source and drain regions are formed using blanket implants of two different conductivities into a semiconductor substrate having two contiguous wells of opposite conductivity type. By blanket implanting a first dopant into both wells, and then selectively implanting a second dopant, the diffusion of the second dopant is partially suppressed by the first dopant. The partial suppression of first dopant results in shallow implants being formed. Also disclosed is a process for forming contact openings and contact implants.
摘要翻译：一种使用单个掩模步骤制造CMOS结构以定义用于N沟道和P沟道器件的轻掺杂源极和漏极区的工艺。该过程形成邻近门结构和至少一个逆行井的一次性间隔物。使用不同能级的一种或多种带电离子形成逆行阱。此外，使用具有两个不同导电性的覆盖植入物形成具有相反导电类型的两个连续的阱的半导体衬底，形成重掺杂源极和漏极区域。通过将第一掺杂剂一次性地注入两个孔中，然后选择性地注入第二掺杂剂，第二掺杂剂的扩散部分被第一掺杂剂抑制。第一掺杂物的部分抑制导致形成浅的植入物。还公开了一种用于形成接触开口和接触植入物的方法。

5. 发明授权

US5654213A Method for fabricating a CMOS device 失效
标题翻译： CMOS器件制造方法
公开(公告)号：US5654213A
公开(公告)日：1997-08-05
申请号：US538533
申请日：1995-10-03
申请人： Jeong Yeol Choi , Chung-Jen Chien , Chung-Chyung Han , Chuen-Der Lien
发明人： Jeong Yeol Choi , Chung-Jen Chien , Chung-Chyung Han , Chuen-Der Lien
IPC分类号： H01L21/762 , H01L21/8238 , H01L21/265
CPC分类号： H01L21/823864 , H01L21/76202 , H01L21/823814 , H01L21/823871 , H01L21/823892
摘要： A process for fabricating a CMOS structure using a single masking step to define lightly-doped source and drain regions for both N- and P-channel devices. The process forms disposable spacers adjacent to gate structures and at least one retrograde well. Retrograde wells are formed using one or more charged ions at different energy levels. In addition, heavily-doped source and drain regions are formed using blanket implants of two different conductivities into a semiconductor substrate having two contiguous wells of opposite conductivity type. By blanket implanting a first dopant into both wells, and then selectively implanting a second dopant, the diffusion of the second dopant is partially suppressed by the first dopant. The partial suppression of first dopant results in shallow implants being formed. Also disclosed is a process for forming contact openings and contact implants.
摘要翻译：一种使用单个掩模步骤制造CMOS结构以定义用于N沟道和P沟道器件的轻掺杂源极和漏极区的工艺。该过程形成邻近门结构和至少一个逆行井的一次性间隔物。使用不同能级的一种或多种带电离子形成逆行阱。此外，使用具有两个不同导电性的覆盖植入物形成具有相反导电类型的两个连续的阱的半导体衬底，形成重掺杂源极和漏极区域。通过将第一掺杂剂一次性地注入两个孔中，然后选择性地注入第二掺杂剂，第二掺杂剂的扩散部分被第一掺杂剂抑制。第一掺杂物的部分抑制导致形成浅的植入物。还公开了一种用于形成接触开口和接触植入物的方法。

6. 发明申请

US20120017989A1 Metal and metal oxide surface texturing 审中-公开
标题翻译：金属和金属氧化物表面纹理
公开(公告)号：US20120017989A1
公开(公告)日：2012-01-26
申请号：US13216402
申请日：2011-08-24
申请人： Pai-Chun Chang , Chung-Jen Chien , Pengfel Qi
发明人： Pai-Chun Chang , Chung-Jen Chien , Pengfel Qi
IPC分类号： H01L31/0232 , C25D5/34 , C25D5/48
CPC分类号： C25D11/04 , C25D11/24 , C25D11/26 , H01L31/02366 , H01L31/0322 , H01L31/0392 , H01L31/03923 , H01L31/03925 , H01L31/056 , H01L31/0749 , H01L31/206 , Y02E10/52 , Y02E10/541 , Y02P70/521
摘要： A method of texturing a metal provides a metal with a thickness of 50 to 400 μm. The metal is anodized, etched and then textured in a first texturing step to produce a first textured surface of the metal. A textured metal is produced with a dimpled surface of dimples with diameters of 5 nm to 2 and a depth of from 2 nm to 2 μm.
摘要翻译：对金属进行纹理化的方法提供厚度为50〜400μm的金属。在第一纹理化步骤中对金属进行阳极氧化，蚀刻和纹理化以产生金属的第一纹理表面。产生纹理金属，其具有直径为5nm至2μm，深度为2nm至2μm的凹坑的凹坑表面。

7. 发明授权

US06215701B1 Nonvolatile memory cell structure for integration with semiconductor logic devices and method of using same 失效
标题翻译：用于与半导体逻辑器件集成的非易失性存储单元结构及其使用方法
公开(公告)号：US06215701B1
公开(公告)日：2001-04-10
申请号：US09218026
申请日：1998-12-22
申请人： Chingchi Yao , Chung-Jen Chien
发明人： Chingchi Yao , Chung-Jen Chien
IPC分类号： G11C1600
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors provides a floating gate for storing data while the other transistor is provided with a control gate for selecting the memory cell, and is connected with a bit line for reading data stored in the cell. The nonvolatile memory cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the nonvolatile memory cell may be fabricated in a logic device with the standard processes used to produce the logic device.
摘要翻译：非易失性存储单元包括第一和第二MOS晶体管，例如CMOS单元中的PMOS晶体管和NMOS晶体管。两个晶体管之一提供用于存储数据的浮动栅极，而另一个晶体管设置有用于选择存储器单元的控制栅极，并且与用于读取存储在单元中的数据的位线连接。非易失性存储单元可以使用形成在门阵列中的PMOS和NMOS晶体管单元集成到诸如CMOS门阵列的逻辑器件中。在这种情况下，非易失性存储单元可以用用于产生逻辑器件的标准工艺制成逻辑器件。

8. 发明授权

US06201725B1 Nonvolatile memory cell structure for integration with semiconductor logic devices and method of using same 失效
公开(公告)号：US06201725B1
公开(公告)日：2001-03-13
申请号：US09592260
申请日：2000-06-12
申请人： Chingchi Yao , Chung-Jen Chien
发明人： Chingchi Yao , Chung-Jen Chien
IPC分类号： G11C502
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors provides a floating gate for storing data while the other transistor is provided with a control gate for selecting the memory cell, and is connected with a bit line for reading data stored in the cell. The nonvolatile memory cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the nonvolatile memory cell may be fabricated in a logic device with the standard processes used to produce the logic device.

9. 发明授权

US6097048A Dynamic random access memory cell suitable for integration with semiconductor logic devices 失效
标题翻译：适合与半导体逻辑器件集成的动态随机存取存储器
公开(公告)号：US6097048A
公开(公告)日：2000-08-01
申请号：US218303
申请日：1998-12-22
申请人： Chingchi Yao , Chung-Jen Chien , Thomas Chao
发明人： Chingchi Yao , Chung-Jen Chien , Thomas Chao
IPC分类号： H01L27/06 , H01L27/108
CPC分类号： H01L27/0629 , H01L27/108 , H01L27/10897
摘要： A dynamic random access memory (DRAM) cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors functions as a switch transistor while the other transistor is configured as a storage capacitor. The DRAM cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the DRAM cell may be fabricated in a logic device with the standard processes used to produce the logic device.
摘要翻译：动态随机存取存储器（DRAM）单元包括第一和第二MOS晶体管，例如CMOS单元中的PMOS晶体管和NMOS晶体管。两个晶体管中的一个用作开关晶体管，而另一个晶体管被配置为存储电容器。可以使用形成在门阵列中的PMOS和NMOS晶体管单元将DRAM单元集成到诸如CMOS门阵列的逻辑器件中。在这种情况下，可以使用用于产生逻辑器件的标准工艺在逻辑器件中制造DRAM单元。

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