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1. 发明申请

US20090319968A1 DESIGN AND VERIFICATION OF 3D INTEGRATED CIRCUITS 有权
标题翻译： 3D集成电路的设计与验证
公开(公告)号：US20090319968A1
公开(公告)日：2009-12-24
申请号：US12141690
申请日：2008-06-18
申请人： Chung-Hsing Wang , Chih Sheng Tsai , Ying-Lin Liu , Kai-Yun Lin
发明人： Chung-Hsing Wang , Chih Sheng Tsai , Ying-Lin Liu , Kai-Yun Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of designing a 3D integrated circuit (3D IC) including providing a first layout corresponding to a first device of a 3D IC and a second layout corresponding to a second device of a 3D IC is provided. A verification, such as LVS or DRC, may be performed not only on each device separately, but may also be performed to ensure proper connectivity between devices. The verification may be performed on a single layout file (e.g., GDS II file) including the interface layer of the first and second die. Dummy feature pattern may be determined for the 3D IC using a layout including the interface layers of the first and second devices.
摘要翻译：提供一种设计3D集成电路（3D IC）的方法，包括提供对应于3D IC的第一设备的第一布局和对应于3D IC的第二设备的第二布局。诸如LVS或DRC之类的验证可以不仅在每个设备上分开执行，而且还可以被执行以确保设备之间的正确连接。可以在包括第一和第二裸片的界面层的单个布局文件（例如，GDS II文件）上执行验证。可以使用包括第一和第二装置的界面层的布局来确定3D IC的虚拟特征图案。

2. 发明授权

US08359554B2 Verification of 3D integrated circuits 有权
标题翻译： 3D集成电路验证
公开(公告)号：US08359554B2
公开(公告)日：2013-01-22
申请号：US13274091
申请日：2011-10-14
申请人： Chung-Hsing Wang , Chih Sheng Tsai , Ying-Lin Liu , Kai-Yun Lin
发明人： Chung-Hsing Wang , Chih Sheng Tsai , Ying-Lin Liu , Kai-Yun Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.
摘要翻译：一种设计和验证3D集成电路（3D IC）的方法，包括提供对应于3D IC的第一设备的第一布局。第一布局包括第一接口层。还提供了对应于3D IC的第二设备的第二布局。第二布局包括第二接口层。通过验证第一和第二界面层来执行3D的验证。验证包括在第一和/或第二接口层上执行设计规则检查（DRC）或布局相对于示意图（LVS）中的至少一个。

3. 发明申请

US20120036489A1 DESIGN AND VERIFICATION OF 3D INTEGRATED CIRCUITS 有权
标题翻译： 3D集成电路的设计与验证
公开(公告)号：US20120036489A1
公开(公告)日：2012-02-09
申请号：US13274091
申请日：2011-10-14
申请人： Chung-Hsing Wang , Chih Sheng Tsai , Ying-Lin Liu , Kai-Yun Lin
发明人： Chung-Hsing Wang , Chih Sheng Tsai , Ying-Lin Liu , Kai-Yun Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of designing and verifying 3D integrated circuits (3D IC) including providing a first layout corresponding to a first device of a 3D IC. The first layout includes a first interface layer. A second layout corresponding to a second device of the 3D IC is also provided. The second layout includes a second interface layer. A verification of the 3D is performed by verifying the first and second interface layers. The verification includes performing at least one of a design rule check (DRC) or a layout-versus-schematic (LVS) on the first and/or second interface layers.
摘要翻译：一种设计和验证3D集成电路（3D IC）的方法，包括提供对应于3D IC的第一设备的第一布局。第一布局包括第一接口层。还提供了对应于3D IC的第二设备的第二布局。第二布局包括第二接口层。通过验证第一和第二界面层来执行3D的验证。验证包括在第一和/或第二接口层上执行设计规则检查（DRC）或布局相对于示意图（LVS）中的至少一个。

4. 发明授权

US08060843B2 Verification of 3D integrated circuits 有权
标题翻译： 3D集成电路验证
公开(公告)号：US08060843B2
公开(公告)日：2011-11-15
申请号：US12141690
申请日：2008-06-18
申请人： Chung-Hsing Wang , Chih Sheng Tsai , Ying-Lin Liu , Kai-Yun Lin
发明人： Chung-Hsing Wang , Chih Sheng Tsai , Ying-Lin Liu , Kai-Yun Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method of designing a 3D integrated circuit (3D IC) including providing a first layout corresponding to a first device of a 3D IC and a second layout corresponding to a second device of a 3D IC is provided. A verification, such as LVS or DRC, may be performed not only on each device separately, but may also be performed to ensure proper connectivity between devices. The verification may be performed on a single layout file (e.g., GDS II file) including the interface layer of the first and second die. Dummy feature pattern may be determined for the 3D IC using a layout including the interface layers of the first and second devices.
摘要翻译：提供一种设计3D集成电路（3D IC）的方法，包括提供对应于3D IC的第一设备的第一布局和对应于3D IC的第二设备的第二布局。诸如LVS或DRC之类的验证可以不仅在每个设备上分开执行，而且还可以被执行以确保设备之间的正确连接。可以在包括第一和第二裸片的界面层的单个布局文件（例如，GDS II文件）上执行验证。可以使用包括第一和第二装置的界面层的布局来确定3D IC的虚拟特征图案。

5. 发明授权

US09672315B2 Optimization for circuit migration 有权
公开(公告)号：US09672315B2
公开(公告)日：2017-06-06
申请号：US12846594
申请日：2010-07-29
申请人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu “Alex” Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
发明人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu “Alex” Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5068 , G06F17/5072
摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

6. 发明申请

US20100259308A1 Clock Circuit and Method for Pulsed Latch Circuits 有权
标题翻译：脉冲锁存电路的时钟电路和方法
公开(公告)号：US20100259308A1
公开(公告)日：2010-10-14
申请号：US12688741
申请日：2010-01-15
申请人： Chung-Hsing Wang , Chih-Chieh Chen , Chih Sheng Tsai , Shu Yi Ying
发明人： Chung-Hsing Wang , Chih-Chieh Chen , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , G06F1/04
摘要： Circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.
摘要翻译：描述了提供用于脉冲锁存电路的脉冲时钟信号的电路和方法。可变脉冲发生器耦合以响应于控制信号和时钟输入信号形成脉冲时钟输出。反馈回路具有脉冲监视器和脉冲控制电路。脉冲时钟信号的采样由脉冲监视器拍摄，并且以图案的形式形成输出。脉冲控制电路接收监视器的输出并确定其是否匹配预定模式。调整控制信号以自适应调整脉冲时钟信号。反馈回路可以连续工作。在替代实施例中，反馈回路可以断电。公开了用于自适应地控制脉冲时钟信号的方法。

7. 发明授权

US08232824B2 Clock circuit and method for pulsed latch circuits 有权
标题翻译：脉冲锁存电路的时钟电路和方法
公开(公告)号：US08232824B2
公开(公告)日：2012-07-31
申请号：US12688741
申请日：2010-01-15
申请人： Chung-Hsing Wang , Chih-Chieh Chen , Chih Sheng Tsai , Shu Yi Ying
发明人： Chung-Hsing Wang , Chih-Chieh Chen , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , G06F1/04
摘要： Circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.
摘要翻译：描述了提供用于脉冲锁存电路的脉冲时钟信号的电路和方法。可变脉冲发生器耦合以响应于控制信号和时钟输入信号形成脉冲时钟输出。反馈回路具有脉冲监视器和脉冲控制电路。脉冲时钟信号的采样由脉冲监视器拍摄，并且以图案的形式形成输出。脉冲控制电路接收监视器的输出并确定其是否匹配预定模式。调整控制信号以自适应调整脉冲时钟信号。反馈回路可以连续工作。在替代实施例中，反馈回路可以断电。公开了用于自适应地控制脉冲时钟信号的方法。

8. 发明申请

US20110035717A1 Design Optimization for Circuit Migration 有权
标题翻译：电路迁移的设计优化
公开(公告)号：US20110035717A1
公开(公告)日：2011-02-10
申请号：US12846594
申请日：2010-07-29
申请人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu Alex Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
发明人： Lee-Chung Lu , Yi-Kan Cheng , Chung-Hsing Wang , Chen-Fu Alex Huang , Hsiao-Shu Chao , Chin-Yu Chiang , Ho Che Yu , Chih Sheng Tsai , Shu Yi Ying
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/505 , G06F17/5068 , G06F17/5072
摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.
摘要翻译：本发明的实施例是一种用于提供集成电路布局的经调整的电子表示的计算机程序产品。计算机程序产品具有其上体现计算机程序的介质。此外，计算机程序包括用于从完整节点网表提供全节点单元的计算机程序代码，用于缩放全节点单元以提供收缩节点单元的计算机程序代码，用于提供全节点单元的定时性能的计算机程序代码和收缩节点单元，用于将全节点单元的定时性能与收缩节点单元的定时性能进行比较的计算机程序代码以及用于提供第一网表的计算机程序代码。

9. 发明授权

US07184278B2 Electronic apparatus and shielding structure for heat dissipation openings 有权
标题翻译：用于散热开口的电子设备和屏蔽结构
公开(公告)号：US07184278B2
公开(公告)日：2007-02-27
申请号：US11159319
申请日：2005-06-23
申请人： Chih Sheng Tsai
发明人： Chih Sheng Tsai
IPC分类号： H05K9/00
CPC分类号： G06F1/203
摘要： An electrical apparatus includes a housing, a shielding plate, a first elastic element, and a second elastic element. In this case, the housing has at least one heat dissipation opening. The shielding plate has at least one first hole, a first sidewall and a second sidewall. The shielding plate is disposed parallel to at least one part of the housing. When the shielding plate is moved, the first hole and the heat dissipation opening are aligned. At least one part of the first elastic element contacts the first sidewall. The first elastic element is made of a shape memory alloy. At least one part of the second elastic element contacts the second sidewall. The shielding plate is movable between the first elastic element and the second elastic element.
摘要翻译：电气设备包括壳体，屏蔽板，第一弹性元件和第二弹性元件。在这种情况下，壳体具有至少一个散热开口。屏蔽板具有至少一个第一孔，第一侧壁和第二侧壁。屏蔽板平行于壳体的至少一部分设置。当屏蔽板移动时，第一孔和散热开口对齐。第一弹性元件的至少一部分接触第一侧壁。第一弹性元件由形状记忆合金制成。第二弹性元件的至少一部分接触第二侧壁。屏蔽板可在第一弹性元件和第二弹性元件之间移动。

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