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1. 发明申请

US20080233765A1 Method for enhancing adhesion between layers 有权
标题翻译：提高层间粘附性的方法
公开(公告)号：US20080233765A1
公开(公告)日：2008-09-25
申请号：US11727133
申请日：2007-03-23
申请人： Chung-Chi Ko , Lih-Ping Li , Yung-Cheng Lu , Hui-Lin Chang , Chih-Hsien Lin
发明人： Chung-Chi Ko , Lih-Ping Li , Yung-Cheng Lu , Hui-Lin Chang , Chih-Hsien Lin
IPC分类号： H01L21/469 , H01L21/31
CPC分类号： H01L21/31633 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/76832 , H01L21/76834 , H01L21/76835
摘要： A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.
摘要翻译：一种新颖的方法，用于在半导体晶片衬底上的集成电路制造过程中，在金属互连的形成过程中，增强相邻电介质层之间的界面附着力，特别是在蚀刻停止层和具有低介电常数（k）的上覆电介质层之间。该方法可以包括提供衬底，在衬底上提供蚀刻停止层，在蚀刻停止层上提供富氧介电预置层，并在富氧电介质预层上提供主要电介质层。然后在电介质层中形成金属互连。在蚀刻停止层和上部电介质层之间的富氧介电预层防止或最小化由金属层和/或芯片封装的化学机械平坦化引起的应力引起的层的剥离和破裂。

2. 发明授权

US07897505B2 Method for enhancing adhesion between layers in BEOL fabrication 有权
标题翻译：增加BEOL制作中层间粘附性的方法
公开(公告)号：US07897505B2
公开(公告)日：2011-03-01
申请号：US11727133
申请日：2007-03-23
申请人： Chung-Chi Ko , Lih-Ping Li , Yung-Cheng Lu , Hui-Lin Chang , Chih-Hsien Lin
发明人： Chung-Chi Ko , Lih-Ping Li , Yung-Cheng Lu , Hui-Lin Chang , Chih-Hsien Lin
IPC分类号： H01L21/4763 , H01L21/00
CPC分类号： H01L21/31633 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/76832 , H01L21/76834 , H01L21/76835
摘要： A novel method for enhancing interface adhesion between adjacent dielectric layers, particularly between an etch stop layer and an overlying dielectric layer having a low dielectric constant (k) in the formation of metal interconnects during the fabrication of integrated circuits on semiconductor wafer substrates. The method may include providing a substrate, providing an etch stop layer on the substrate, providing an oxygen-rich dielectric pre-layer on the etch stop layer and providing a major dielectric layer on the oxygen-rich dielectric pre-layer. Metal interconnects are then formed in the dielectric layers. The oxygen-rich dielectric pre-layer between the etch stop layer and the upper dielectric layer prevents or minimizes peeling and cracking of the layers induced by stresses that are caused by chemical mechanical planarization of metal layers and/or chip packaging.
摘要翻译：一种新颖的方法，用于在半导体晶片衬底上的集成电路制造过程中，在金属互连的形成过程中，增强相邻电介质层之间的界面附着力，特别是在蚀刻停止层和具有低介电常数（k）的上覆电介质层之间。该方法可以包括提供衬底，在衬底上提供蚀刻停止层，在蚀刻停止层上提供富氧介电预置层，并在富氧电介质预层上提供主要电介质层。然后在电介质层中形成金属互连。在蚀刻停止层和上部电介质层之间的富氧介电预层防止或最小化由金属层和/或芯片封装的化学机械平坦化引起的应力引起的层的剥离和破裂。

3. 发明授权

US06756321B2 Method for forming a capping layer over a low-k dielectric with improved adhesion and reduced dielectric constant 有权
标题翻译：在低k电介质上形成覆盖层的方法，其具有改善的粘附性和降低的介电常数
公开(公告)号：US06756321B2
公开(公告)日：2004-06-29
申请号：US10264398
申请日：2002-10-05
申请人： Chung-Chi Ko , Yung-Cheng Lu , Lain-Jong Li , Lih-Ping Li , Yu-Huei Chen , Shu-E Ku
发明人： Chung-Chi Ko , Yung-Cheng Lu , Lain-Jong Li , Lih-Ping Li , Yu-Huei Chen , Shu-E Ku
IPC分类号： H01L2131
CPC分类号： H01L21/02362 , H01L21/02118 , H01L21/02126 , H01L21/022 , H01L21/02211 , H01L21/02271 , H01L21/02274 , H01L21/312 , H01L21/3122 , H01L21/3127 , H01L21/3185 , H01L21/76801 , H01L21/76807 , H01L21/76832 , H01L21/76835 , Y10S438/902
摘要： A method for forming a capping layer for improved adhesion with an underlying insulating layer in a multiple layer semiconductor device manufacturing process including providing a semiconductor wafer including a process surface comprising a dielectric insulating layer; and, providing a capping layer overlying the dielectric insulating layer according to a chemical vapor deposition CVD) process. The capping layer of the present invention has improved adhesion and a reduced dielectric constant with comparable current leakage compared to capping layers of the prior art.
摘要翻译：一种用于在多层半导体器件制造工艺中形成用于提高与底层绝缘层的粘附性的覆盖层的方法，包括提供包括包括介电绝缘层的工艺表面的半导体晶片; 并且根据化学气相沉积CVD提供覆盖介电绝缘层的覆盖层）。与现有技术的覆盖层相比，本发明的覆盖层具有改善的粘附性和降低的介电常数，具有相当的电流泄漏。

4. 发明授权

US06602780B2 Method for protecting sidewalls of etched openings to prevent via poisoning 有权
标题翻译：用于保护蚀刻开口的侧壁以防止通过中毒的方法
公开(公告)号：US06602780B2
公开(公告)日：2003-08-05
申请号：US09947788
申请日：2001-09-06
申请人： Tsu Shih , Yung-Cheng Lu , Lih Ping Li , Tien-I Bao , Chung Chi Ko
发明人： Tsu Shih , Yung-Cheng Lu , Lih Ping Li , Tien-I Bao , Chung Chi Ko
IPC分类号： H01L214763
CPC分类号： H01L21/76807 , H01L21/76831 , H01L2221/1057
摘要： A method for forming a protective oxide liner to reduce a surface reflectance including providing a hydrophilic insulating layer over a conductive layer; providing an anti-reflectance coating (ARC) layer over the hydrophilic insulating layer; providing an etching stop layer over the anti-reflectance coating (ARC) layer; photolithographically defining a pattern on a surface of the etching stop layer for etching; anisotropically etching at least one etch opening extending at least partially through a thickness of the hydrophilic insulating layer; depositing an oxide liner such that the sidewalls and bottom portion of the at least one etch opening and said surface are covered by the oxide liner; and, removing the oxide liner from aid surface according to a chemical mechanical (CMP) process to a surface reflectance.
摘要翻译：一种用于形成保护性氧化物衬垫以减少表面反射率的方法，包括在导电层上提供亲水性绝缘层; 在所述亲水绝缘层上提供抗反射涂层（ARC）层; 在抗反射涂层（ARC）层上提供蚀刻停止层; 在蚀刻停止层的表面上光刻地限定图案用于蚀刻; 各向异性蚀刻至少一个至少部分延伸穿过亲水性绝缘层的厚度的蚀刻开口; 沉积氧化物衬里，使得所述至少一个蚀刻开口和所述表面的侧壁和底部被所述氧化物衬垫覆盖; 并且根据化学机械（CMP）工艺将氧化物衬垫从辅助表面去除到表面反射率。

5. 发明授权

US07456093B2 Method for improving a semiconductor device delamination resistance 有权
标题翻译：提高半导体器件耐分层性的方法
公开(公告)号：US07456093B2
公开(公告)日：2008-11-25
申请号：US10884719
申请日：2004-07-03
申请人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
发明人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L23/53295 , H01L21/76801 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/3135 , H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.
摘要翻译：具有改进的分层耐受性的半导体器件及其形成方法包括提供包含具有最上蚀刻停止层的金属化层的半导体晶片的方法; 在所述蚀刻停止层上形成至少一个附着促进层; 以及在所述至少一个附着促进层上形成金属间电介质（IMD）层。

6. 发明申请

US20060003572A1 Method for improving a semiconductor device delamination resistance 有权
标题翻译：提高半导体器件耐分层性的方法
公开(公告)号：US20060003572A1
公开(公告)日：2006-01-05
申请号：US10884719
申请日：2004-07-03
申请人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
发明人： Pi-Tsung Chen , Keng-Chu Lin , Hui-Lin Chang , Lih-Ping Li , Tien-I Bao , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53295 , H01L21/76801 , H01L21/76802 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/3135 , H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with improved resistance to delamination and method for forming the same the method including providing a semiconductor wafer comprising a metallization layer with an uppermost etch stop layer; forming at least one adhesion promoting layer on the etch stop layer; and, forming an inter-metal dielectric (IMD) layer on the at least one adhesion promoting layer.
摘要翻译：具有改进的分层耐受性的半导体器件及其形成方法包括提供包含具有最上蚀刻停止层的金属化层的半导体晶片的方法; 在所述蚀刻停止层上形成至少一个附着促进层; 以及在所述至少一个附着促进层上形成金属间电介质（IMD）层。

7. 发明授权

US07312531B2 Semiconductor device and fabrication method thereof 有权
公开(公告)号：US07312531B2
公开(公告)日：2007-12-25
申请号：US11261200
申请日：2005-10-28
申请人： Hui-Lin Chang , Yung-Cheng Lu , Chung-Chi Ko , Pi-Tsung Chen , Shau-Lin Shue , Chien-Hsueh Shih , Hung-Wen Su , Ming-Hsing Tsai
发明人： Hui-Lin Chang , Yung-Cheng Lu , Chung-Chi Ko , Pi-Tsung Chen , Shau-Lin Shue , Chien-Hsueh Shih , Hung-Wen Su , Ming-Hsing Tsai
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L23/53276 , H01L21/76849 , H01L21/76852 , H01L21/76879 , H01L21/76885 , H01L23/5226 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer overlies the electrode and the first dielectric layer and substantially comprises Co and M1, wherein M1 is selected from a group consisting of W, P, B, Bi, Ni, and a combination thereof. The second dielectric layer overlies the catalyst layer and comprises an opening exposing parts of the catalyst layer. The carbon nanotubes (CNTs) are disposed on the exposed catalyst layer and electrically connect the electrode.

8. 发明申请

US20070096326A1 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070096326A1
公开(公告)日：2007-05-03
申请号：US11261200
申请日：2005-10-28
申请人： Hui-Lin Chang , Yung-Cheng Lu , Chung-Chi Ko , Pi-Tsung Chen , Shau-Lin Shue , Chien-Hsueh Shih , Hung-Wen Su , Ming-Hsing Tsai
发明人： Hui-Lin Chang , Yung-Cheng Lu , Chung-Chi Ko , Pi-Tsung Chen , Shau-Lin Shue , Chien-Hsueh Shih , Hung-Wen Su , Ming-Hsing Tsai
IPC分类号： H01L23/48
CPC分类号： H01L23/53276 , H01L21/76849 , H01L21/76852 , H01L21/76879 , H01L21/76885 , H01L23/5226 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer overlies the electrode and the first dielectric layer and substantially comprises Co and M1, wherein M1 is selected from a group consisting of W, P, B, Bi, Ni, and a combination thereof. The second dielectric layer overlies the catalyst layer and comprises an opening exposing parts of the catalyst layer. The carbon nanotubes (CNTs) are disposed on the exposed catalyst layer and electrically connect the electrode.
摘要翻译：半导体器件及其制造方法。这些器件包括衬底，催化剂层，第二介电层和碳纳米管（CNT）。衬底包括具有嵌入其中的电极的上覆的第一介电层。催化剂层覆盖电极和第一介电层，并且基本上包括Co和M 1，其中M 1选自W，P，B，Bi ，Ni及其组合。第二电介质层覆盖在催化剂层上并且包括露出催化剂层的部分的开口。碳纳米管（CNT）设置在暴露的催化剂层上并电连接电极。

9. 发明申请

US20050048795A1 Method for ultra low-K dielectric deposition 审中-公开
标题翻译：超低K电介质沉积方法
公开(公告)号：US20050048795A1
公开(公告)日：2005-03-03
申请号：US10649566
申请日：2003-08-27
申请人： Chung-Chi Ko , Yung-Cheng Lu , Tien-I Bao , Hui-Lin Chang , Syun-Ming Jang
发明人： Chung-Chi Ko , Yung-Cheng Lu , Tien-I Bao , Hui-Lin Chang , Syun-Ming Jang
IPC分类号： H01L21/312 , H01L21/768 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02271 , H01L21/02126 , H01L21/02282 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/312 , H01L21/3121 , H01L21/7682
摘要： The present invention provides a method of forming a semiconductor structure having an ultra low-K dielectric material that adheres well to the substrate. The method includes depositing a low-K material on the top surface of a substrate at a low temperature of no more than 250° by a CVD or spin-on process. The dielectric material is then cured by placing the substrate with the dielectric film in an environment where the temperature is regulated at about 400° or less as the dielectric film is being subjected to a plasma treatment or an E-beam treatment or UV treatment. The environment may further include one or more gases or a mixture of gases selected from the group consisting of H2, N2, NH3, CO2, all hydride gases and a mixture of these gases.
摘要翻译：本发明提供一种形成半导体结构的方法，所述半导体结构具有与基底良好粘合的超低K电介质材料。该方法包括通过CVD或旋涂工艺在低于250°的低温下在衬底的顶表面上沉积低K材料。然后通过将介质膜放置在介质膜经受等离子体处理或电子束处理或UV处理的温度调节在约400°或更小的环境中来固化电介质材料。环境可以进一步包括选自H 2，N 2，NH 3，CO 2，所有氢化物气体和这些气体的混合物的一种或多种气体或气体混合物。

10. 发明授权

US08987085B2 Methods for improving uniformity of cap layers 有权
标题翻译：改善盖层均匀性的方法
公开(公告)号：US08987085B2
公开(公告)日：2015-03-24
申请号：US11524000
申请日：2006-09-20
申请人： Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
发明人： Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
IPC分类号： H01L21/768 , H01L21/02 , H01L21/3105
CPC分类号： H01L21/76849 , H01L21/02074 , H01L21/3105 , H01L21/76826
摘要： A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.
摘要翻译：形成集成电路的方法包括提供半导体衬底，在半导体衬底上形成金属化层，其中金属化层包括低k电介质层中的金属特征并且从低k电介质层的顶表面延伸进入低k电介质层，对低k电介质层进行处理以形成亲水性顶表面，以及在溶液中的金属特征上镀覆盖层。

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