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1. 发明授权

US08987085B2 Methods for improving uniformity of cap layers 有权
标题翻译：改善盖层均匀性的方法
公开(公告)号：US08987085B2
公开(公告)日：2015-03-24
申请号：US11524000
申请日：2006-09-20
申请人： Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
发明人： Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
IPC分类号： H01L21/768 , H01L21/02 , H01L21/3105
CPC分类号： H01L21/76849 , H01L21/02074 , H01L21/3105 , H01L21/76826
摘要： A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.
摘要翻译：形成集成电路的方法包括提供半导体衬底，在半导体衬底上形成金属化层，其中金属化层包括低k电介质层中的金属特征并且从低k电介质层的顶表面延伸进入低k电介质层，对低k电介质层进行处理以形成亲水性顶表面，以及在溶液中的金属特征上镀覆盖层。

2. 发明申请

US20080032472A1 Methods for improving uniformity of cap layers 有权
标题翻译：改善盖层均匀性的方法
公开(公告)号：US20080032472A1
公开(公告)日：2008-02-07
申请号：US11524000
申请日：2006-09-20
申请人： Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
发明人： Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
IPC分类号： H01L21/8242
CPC分类号： H01L21/76849 , H01L21/02074 , H01L21/3105 , H01L21/76826
摘要： A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.
摘要翻译：形成集成电路的方法包括提供半导体衬底，在半导体衬底上形成金属化层，其中金属化层包括低k电介质层中的金属特征并且从低k电介质层的顶表面延伸进入低k电介质层，对低k电介质层进行处理以形成亲水性顶表面，以及在溶液中的金属特征上镀覆盖层。

3. 发明授权

US08623760B2 Process for improving copper line cap formation 有权
标题翻译：改善铜线帽形成的工艺
公开(公告)号：US08623760B2
公开(公告)日：2014-01-07
申请号：US13440704
申请日：2012-04-05
申请人： Chien-Hsueh Shih , Minghsing Tsai , Chen-Hua Yu , Ming-Shih Yeh
发明人： Chien-Hsueh Shih , Minghsing Tsai , Chen-Hua Yu , Ming-Shih Yeh
IPC分类号： H01L21/768
CPC分类号： H01L21/76849 , H01L21/02074 , H01L21/3212 , H01L21/32134 , H01L21/76865 , H01L21/76883
摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.
摘要翻译：集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在导线。

4. 发明授权

US08193087B2 Process for improving copper line cap formation 有权
标题翻译：改善铜线帽形成的工艺
公开(公告)号：US08193087B2
公开(公告)日：2012-06-05
申请号：US11605893
申请日：2006-11-28
申请人： Chien-Hsueh Shih , Minghsing Tsai , Chen-Hua Yu , Ming-Shih Yeh
发明人： Chien-Hsueh Shih , Minghsing Tsai , Chen-Hua Yu , Ming-Shih Yeh
IPC分类号： H01L21/768
CPC分类号： H01L21/76849 , H01L21/02074 , H01L21/3212 , H01L21/32134 , H01L21/76865 , H01L21/76883
摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.
摘要翻译：集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在导线。

5. 发明申请

US20070269978A1 Process for improving copper line cap formation 有权
标题翻译：改善铜线帽形成的工艺
公开(公告)号：US20070269978A1
公开(公告)日：2007-11-22
申请号：US11605893
申请日：2006-11-28
申请人： Chien-Hsueh Shih , Minghsing Tsai , Chen-Hua Yu , Ming-Shih Yeh
发明人： Chien-Hsueh Shih , Minghsing Tsai , Chen-Hua Yu , Ming-Shih Yeh
IPC分类号： H01L21/768
CPC分类号： H01L21/76849 , H01L21/02074 , H01L21/3212 , H01L21/32134 , H01L21/76865 , H01L21/76883
摘要： An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.
摘要翻译：集成电路包括半导体衬底，半导体衬底上的低k电介质层，低k电介质层中的第一开口，第一开口中的第一扩散阻挡层，覆盖第一开口中的低k电介质层开口，其中所述第一扩散阻挡层具有连接到侧壁部分的底部，并且其中所述侧壁部分具有靠近所述低k电介质层的顶表面的顶表面。集成电路还包括填充第一开口的导电线，其中导电线具有比扩散阻挡层的侧壁部分的顶表面低的顶表面，以及导电线上的金属盖，并且仅在直接在导线。

6. 发明申请

US20110024908A1 LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE 有权
标题翻译：低电阻高可靠性接触半导体器件的金属线结构
公开(公告)号：US20110024908A1
公开(公告)日：2011-02-03
申请号：US12845852
申请日：2010-07-29
申请人： Hsiang-Huan Lee , Ming Han Lee , Ming-Shih Yeh , Chen-Hua Yu , Shau-Lin Shue
发明人： Hsiang-Huan Lee , Ming Han Lee , Ming-Shih Yeh , Chen-Hua Yu , Shau-Lin Shue
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53238 , H01L21/28562 , H01L21/76846 , H01L21/76867 , H01L21/76873 , H01L21/76883 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.
摘要翻译：上述结构和方法提供了提高互连可靠性和电阻率的机制。通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。

7. 发明申请

US20090218693A1 LOW RESISTANCE HIGH RELIABILITY CONTACT VIA AND METAL LINE STRUCTURE FOR SEMICONDUCTOR DEVICE 有权
标题翻译：低电阻高可靠性接触半导体器件的金属线结构
公开(公告)号：US20090218693A1
公开(公告)日：2009-09-03
申请号：US12112405
申请日：2008-04-30
申请人： Hsiang-Huan Lee , Ming Han Lee , Ming-Shih Yeh , Chen-Hua Yu
发明人： Hsiang-Huan Lee , Ming Han Lee , Ming-Shih Yeh , Chen-Hua Yu
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76846 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor contact structure includes a copper plug formed within a dual damascene, single damascene or other opening formed in a dielectric material and includes a composite barrier layer between the copper plug and the sidewalls and bottom of the opening. The composite barrier layer preferably includes an ALD TaN layer disposed on the bottom and along the sides of the opening although other suitable ALD layers may be used. A barrier material is disposed between the copper plug and the ALD layer. The barrier layer may be a Mn-based barrier layer, a Cr-based barrier layer, a V-based barrier layer, a Nb-based barrier layer, a Ti-based barrier layer, or other suitable barrier layers.
摘要翻译：半导体接触结构包括形成在双镶嵌，单镶嵌或形成在电介质材料中的其它开口的铜塞，并且包括铜塞与开口的侧壁和底部之间的复合阻挡层。复合阻挡层优选地包括设置在开口的底部和沿着开口的侧面的ALD TaN层，尽管可以使用其它合适的ALD层。阻挡材料设置在铜塞和ALD层之间。阻挡层可以是基于Mn的阻挡层，Cr基阻挡层，V基阻挡层，Nb基阻挡层，Ti基阻挡层或其它合适的阻挡层。

8. 发明申请

US20090117731A1 SEMICONDUCTOR INTERCONNECTION STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译：半导体互连结构及其制造方法
公开(公告)号：US20090117731A1
公开(公告)日：2009-05-07
申请号：US11934005
申请日：2007-11-01
申请人： Chen-Hua Yu , Shau-Lin Shue , Chien-Hsueh Shih , Ming-Shih Yeh , Ming-Han Lee
发明人： Chen-Hua Yu , Shau-Lin Shue , Chien-Hsueh Shih , Ming-Shih Yeh , Ming-Han Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L21/76856 , H01L21/76867 , H01L21/76873 , H01L21/76877 , H01L2221/1089
摘要： A semiconductor interconnection structure is manufactured as follows. First, a substrate with a first dielectric layer and a second dielectric layer is formed. Subsequently, an opening is formed in the second dielectric layer. A thin metal layer and a seed layer are formed in sequence on the surface of the second dielectric layer in the opening, wherein the metal layer comprises at least one metal species having phase segregation property of a second conductor. The wafer of the substrate is subjected to a thermal treatment, by which most of the metal species in the metal layer at a bottom of the opening is diffused to a top surface of the second conductor to form a metal-based oxide layer. Afterwards, the wafer is subjected to planarization, so as to remove the second conductor outside the opening.
摘要翻译：如下制造半导体互连结构。首先，形成具有第一介电层和第二介质层的基板。随后，在第二电介质层中形成开口。在开口中的第二电介质层的表面上依次形成薄金属层和种子层，其中金属层包含至少一种具有第二导体的相分离特性的金属物质。对基板的晶片进行热处理，通过该热处理，开口底部的金属层中的大部分金属物质扩散到第二导体的顶表面，形成金属基氧化物层。然后，对晶片进行平面化处理，以便将开口外的第二导体移除。

9. 发明授权

US07354856B2 Method for forming dual damascene structures with tapered via portions and improved performance 有权
标题翻译：用于形成具有锥形通孔部分的双镶嵌结构和改进的性能的方法
公开(公告)号：US07354856B2
公开(公告)日：2008-04-08
申请号：US11071104
申请日：2005-03-04
申请人： Ming-Shih Yeh , Ming-Hsing Tsai , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Shih Yeh , Ming-Hsing Tsai , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/44
CPC分类号： H01L21/76804 , H01L21/31144 , H01L21/314 , H01L21/76808 , Y10S438/978
摘要： The manufacture of damascene structures having improved performance, particularly, but not by way of limitation, dual damascene structures is provided. In one embodiment, a substrate having a conductive layer is formed in a first insulating layer. A protective layer is formed above the conductive layer. An etching stop layer is formed above the protective layer and the first insulating layer. A second insulating layer is formed above the etching stop layer. A first patterned photoresist layer is formed above the second insulating layer, the first patterned photoresist layer having a first pattern. The first pattern is etched into the second insulating layer and the etching stop layer to form a first opening. A via plug is filled at least partially in the first opening. An anti-reflective coating (ARC) layer is formed above the second insulating layer. A second patterned photoresist layer is formed above the ARC layer, the second photoresist layer having a second pattern. The second pattern is etched into portions of the via plug, second insulation layer, and the ARC layer to form a second opening, wherein a substantially tapered sidewall portion is formed at the interface of the first and second openings.
摘要翻译：提供了具有改进的性能，特别但非限制性的双镶嵌结构的镶嵌结构的制造。在一个实施例中，具有导电层的衬底形成在第一绝缘层中。在导电层上形成保护层。在保护层和第一绝缘层上方形成蚀刻停止层。在蚀刻停止层上形成第二绝缘层。第一图案化光致抗蚀剂层形成在第二绝缘层之上，第一图案化光致抗蚀剂层具有第一图案。将第一图案蚀刻到第二绝缘层和蚀刻停止层中以形成第一开口。通孔塞至少部分地填充在第一开口中。在第二绝缘层上方形成抗反射涂层（ARC）层。第二图案化光致抗蚀剂层形成在ARC层上方，第二光致抗蚀剂层具有第二图案。第二图案被蚀刻到通孔塞，第二绝缘层和ARC层的部分中以形成第二开口，其中在第一和第二开口的界面处形成大致锥形的侧壁部分。

10. 发明授权

US08432040B2 Interconnection structure design for low RC delay and leakage 有权
标题翻译：低RC延迟和泄漏的互连结构设计
公开(公告)号：US08432040B2
公开(公告)日：2013-04-30
申请号：US11444629
申请日：2006-06-01
申请人： Chen-Hua Yu , Ming-Shih Yeh
发明人： Chen-Hua Yu , Ming-Shih Yeh
IPC分类号： H01L29/41
CPC分类号： H01L21/76816 , H01L21/76807 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An interconnection structure for integrated circuits having reduced RC delay and leakage is provided. The interconnection structure includes a first conductive line in a first dielectric layer, a second dielectric layer over the first dielectric layer and the first conductive line, and a dual damascene structure in the second dielectric layer. The dual damascene structure includes a second conductive line and a via between and adjoining the first and the second conductive lines, wherein the second conductive line comprises a first portion directly over and adjoining the via, and a second portion having no underlying and adjoining vias. The second portion has a second width less than a first width of the first portion.
摘要翻译：提供了具有减小的RC延迟和泄漏的集成电路的互连结构。互连结构包括第一电介质层中的第一导电线，第一电介质层和第一导电线上的第二电介质层，以及第二电介质层中的双镶嵌结构。双镶嵌结构包括第二导电线和在第一和第二导电线之间和之间相邻的通孔，其中第二导电线包括直接在通孔上并邻接通孔的第一部分，以及不具有下面和相邻通孔的第二部分。第二部分具有小于第一部分的第一宽度的第二宽度。

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