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1. 发明申请

US20090001574A1 Multi-chips Stacked package structure 审中-公开
标题翻译：多芯片堆叠封装结构
公开(公告)号：US20090001574A1
公开(公告)日：2009-01-01
申请号：US12036636
申请日：2008-02-25
申请人： Chun-fu FANG , Ming-Hung Su , Yu-Ren Chen
发明人： Chun-fu FANG , Ming-Hung Su , Yu-Ren Chen
IPC分类号： H01L23/538
CPC分类号： H01L25/0657 , H01L24/27 , H01L24/29 , H01L24/31 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L24/85 , H01L2224/05553 , H01L2224/13144 , H01L2224/274 , H01L2224/451 , H01L2224/48227 , H01L2224/49175 , H01L2224/83101 , H01L2224/83191 , H01L2224/83855 , H01L2224/83856 , H01L2224/85 , H01L2225/0651 , H01L2225/06562 , H01L2924/01005 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/00 , H01L2924/00014
摘要： A multi-chips Stacked package structure, wherein a plurality of chips are stacked on the substrate with a rotation so that a plurality of metallic ends and the metal pad on each chip on the substrate can all be exposed; a plurality of metal wires are provided for electrically connecting the plurality of metal pads on the plurality of chips with the plurality metallic ends on the substrate in one wire bonding process; then an encapsulate is provided for covering the plurality of stacked chips, a plurality of metal wires and the plurality of metallic ends on the substrate.
摘要翻译：一种多芯片堆叠封装结构，其中多个芯片以旋转方式堆叠在基板上，使得可以在基板上的每个芯片上的多个金属端和金属焊盘全部暴露; 提供多个金属线，用于在一个引线接合工艺中将多个芯片上的多个金属焊盘与多个金属端部在基板上电连接; 然后提供封装以覆盖多个堆叠的芯片，多个金属线和多个金属端在基板上。

2. 发明授权

US07932531B2 Chip package 有权
标题翻译：芯片封装
公开(公告)号：US07932531B2
公开(公告)日：2011-04-26
申请号：US12506255
申请日：2009-07-21
申请人： Chun-Ying Lin , Ya-Chi Chen , Yu-Ren Chen , I-Hsin Mao
发明人： Chun-Ying Lin , Ya-Chi Chen , Yu-Ren Chen , I-Hsin Mao
IPC分类号： H01L33/00
CPC分类号： H01L21/563 , H01L23/3135 , H01L24/97 , H01L33/642 , H01L2224/16225 , H01L2224/73203 , H01L2224/73204 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/07802 , H01L2924/12041 , H01L2924/12044 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： A chip package includes a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.
摘要翻译：芯片封装包括热增强板，围绕热增强板接触并与热增强板电绝缘，设置在触点和热增强板上的膜状电路层，导电粘合剂层，第一模制件和设置在膜状电路层上的至少一个芯片。导电性粘合剂层设置在触点和通过导电粘合剂层与触点电连接的膜状电路层之间。芯片具有背面，有源表面和设置在其上的许多凸块，并且芯片经由凸块电连接到膜状电路层。第一模制品至少封装热增强板的一部分，导电粘合剂层，触点的一部分和膜状电路层的至少一部分。因此，提高了发光芯片封装的散热效率。

3. 发明申请

US20090072361A1 Multi-Chip Stacked Package Structure 审中-公开
标题翻译：多芯片堆叠封装结构
公开(公告)号：US20090072361A1
公开(公告)日：2009-03-19
申请号：US12122779
申请日：2008-05-19
申请人： Geng-Shin SHEN , Yu-Ren Chen
发明人： Geng-Shin SHEN , Yu-Ren Chen
IPC分类号： H01L23/495
CPC分类号： H01L23/4951 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48095 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00015 , H01L2924/00012
摘要： A multi-chip stacked package structure, comprising: a lead-frame having a top surface a back surface, the inner leads comprising a plurality of first inner leads and a plurality of second inner leads in parallel; a first chip fixedly connected to the back surface of the lead-frame, and the first chip having an active surface and a plurality of first pads adjacent to the central area of the active surface; a plurality of first metal wires electrically connected the first inner leads and the second inner leads and the first pads on the active surface of the first chip; a second chip fixedly connected to the top surface of the lead-frame, and the second chip having an active surface and a plurality of second pads adjacent to the central area of the active surface; a pair of the spacers provided on the thermal fin of the lead-frame; a plurality of second metal wires electrically connected to the top surface of first inner leads and the second inner leads and the second pads on the active surface of the second chip; and a package body encapsulated the first chip, the plurality of metal wires the second chip, the plurality of pads, the first inner leads and the second inner leads and to expose the outer leads.
摘要翻译：一种多芯片堆叠封装结构，包括：具有顶表面的后表面的引线框架，所述内引线包括多个第一内引线和多个第二内引线并联; 第一芯片固定地连接到引线框架的背面，并且第一芯片具有活性表面和与活性表面的中心区域相邻的多个第一焊盘; 多个第一金属线，电连接第一内引线和第二内引线以及第一芯片的有效表面上的第一焊盘; 固定地连接到引线框架的顶表面的第二芯片，并且第二芯片具有活动表面和与活动表面的中心区域相邻的多个第二焊盘; 设置在引线框架的散热片上的一对间隔件; 多个第二金属线，电连接到第一内引线的顶表面，第二内引线和第二芯片的有效表面上的第二焊盘; 以及封装体，其包封所述第一芯片，所述多个金属线，所述第二芯片，所述多个焊盘，所述第一内引线和所述第二内引线，以及露出所述外引线。

4. 发明授权

US08916969B2 Semiconductor devices, packaging methods and structures 有权
标题翻译：半导体器件，封装方法和结构
公开(公告)号：US08916969B2
公开(公告)日：2014-12-23
申请号：US13194606
申请日：2011-07-29
申请人： Yu-Ren Chen , Ming Hung Tseng , Yi-Jen Lai
发明人： Yu-Ren Chen , Ming Hung Tseng , Yi-Jen Lai
IPC分类号： H01L23/48 , H01L23/52 , H01L23/16 , H01L23/00 , H01L23/31 , H01L21/56
CPC分类号： H01L23/562 , H01L21/563 , H01L23/16 , H01L23/3128 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L2224/0401 , H01L2224/05569 , H01L2224/05572 , H01L2224/06155 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13647 , H01L2224/13655 , H01L2224/16225 , H01L2224/73103 , H01L2224/73203 , H01L2224/73204 , H01L2224/81191 , H01L2224/81203 , H01L2224/81815 , H01L2224/92125 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/014 , H01L2224/05552 , H01L2924/00 , H01L2924/00012
摘要： Semiconductor devices, packaging methods and structures are disclosed. In one embodiment, a semiconductor device includes an integrated circuit die with a surface having a peripheral region and a central region. A plurality of bumps is disposed on the surface of the integrated circuit die in the peripheral region. A spacer is disposed on the surface of the integrated circuit die in the central region.
摘要翻译：公开了半导体器件，封装方法和结构。在一个实施例中，半导体器件包括具有周边区域和中心区域的表面的集成电路管芯。在周边区域中的集成电路管芯的表面上设置有多个突起。间隔件设置在中心区域的集成电路管芯的表面上。

5. 发明授权

US07642137B2 Manufacturing method of chip package 有权
标题翻译：芯片封装的制造方法
公开(公告)号：US07642137B2
公开(公告)日：2010-01-05
申请号：US11746654
申请日：2007-05-10
申请人： Chun-Ying Lin , Ya-Chi Chen , Yu-Ren Chen , I-Hsin Mao
发明人： Chun-Ying Lin , Ya-Chi Chen , Yu-Ren Chen , I-Hsin Mao
IPC分类号： H01L21/44
CPC分类号： H01L21/563 , H01L23/3135 , H01L24/97 , H01L33/642 , H01L2224/16225 , H01L2224/73203 , H01L2224/73204 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/07802 , H01L2924/12041 , H01L2924/12044 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： A chip package including a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer is provided. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.
摘要翻译：包括热增强板的芯片封装，在热增强板周围接触并与热增强板电绝缘，设置在触点和热增强板上的膜状电路层，导电粘合剂层，第一模制件和提供设置在膜状电路层上的至少一个芯片。导电性粘合剂层设置在触点和通过导电粘合剂层与触点电连接的膜状电路层之间。芯片具有背面，有源表面和设置在其上的许多凸块，并且芯片经由凸块电连接到膜状电路层。第一模制品至少封装热增强板的一部分，导电粘合剂层，触点的一部分和膜状电路层的至少一部分。因此，提高了发光芯片封装的散热效率。

6. 发明申请

US20090075426A1 Method for Fabricating Multi-Chip Stacked Package 有权
标题翻译：多芯片堆叠封装方法
公开(公告)号：US20090075426A1
公开(公告)日：2009-03-19
申请号：US12134336
申请日：2008-06-06
申请人： Geng-Shin SHEN , Yu-Ren Chen
发明人： Geng-Shin SHEN , Yu-Ren Chen
IPC分类号： H01L21/02
CPC分类号： H01L23/49575 , H01L23/4951 , H01L23/49513 , H01L24/45 , H01L24/48 , H01L2224/16245 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/00015 , H01L2224/05599 , H01L2924/00 , H01L2924/00012
摘要： A multi-chips stacked package method which includes providing a lead frame includes a top surface and a reverse surface formed by a plurality of inner leads and a plurality of outer leads; fixing a first chip on the reverse surface of the lead frame and the active surface of the first chip includes a plurality of first pads closed to the central region; forming a plurality of first metal wires, and the first pads are electrically connected to the first inner leads and the second inner leads by the first metal wires; forming a plurality of metal spacers on the thermal fin of the lead frame; fixing a second chip to electrically connect to the top surface of the first inner leads and the second inner leads; forming a plurality of second metal wires, and the second pads are electrically connected to the top surface of the first inner leads and the second inner leads; and flowing a molding to form an encapsulated material to cover the first chip, the first metal wires, the second chip, the second metal wires, the first inner leads and the second inner leads and the outer leads being exposed.
摘要翻译：包括提供引线框架的多芯片堆叠封装方法包括由多个内引线和多个外引线形成的顶表面和反面; 将第一芯片固定在引线框架的相反表面上，并且第一芯片的有效表面包括多个靠近中心区域的第一焊盘; 形成多个第一金属线，并且所述第一焊盘通过所述第一金属线电连接到所述第一内引线和所述第二内引线; 在引线框架的散热片上形成多个金属间隔物; 固定第二芯片以电连接到第一内引线和第二内引线的顶表面; 形成多个第二金属线，并且所述第二焊盘电连接到所述第一内引线和所述第二内引线的顶表面; 并且使模制件流动以形成覆盖第一芯片的封装材料，第一金属线，第二芯片，第二金属线，第一内引线和第二内引线以及外引线露出。

7. 发明授权

US07348817B2 Circuit and method for generating circuit power on reset signal 有权
标题翻译：用于产生电路上电复位信号的电路和方法
公开(公告)号：US07348817B2
公开(公告)日：2008-03-25
申请号：US11366694
申请日：2006-03-02
申请人： Chun-Yao Laio , Yu-Ren Chen
发明人： Chun-Yao Laio , Yu-Ren Chen
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G06F1/24 , H03K17/161 , H03K17/284
摘要： Disclosed is an improved circuit and method for generating a power on reset signal, the circuit being a two-stage circuit comprising a delay-stage circuit and an output-stage circuit. The delay-stage circuit delays a time for a power on reset signal generated in the output-stage circuit changing from low to high, so that a power voltage having a low rising speed may be normally reset. Further, the two stages provide charging paths and discharging paths so that the power on reset signal may be prevented from changing from high to low when it has changed from low to high, when noises are presented on the power voltage.
摘要翻译：公开了一种用于产生上电复位信号的改进的电路和方法，该电路是包括延迟级电路和输出级电路的两级电路。延迟级电路延迟在输出级电路中产生的上电复位信号从低变为高的时间，使得具有低上升速度的电源电压可以被正常复位。此外，两级提供充电路径和放电路径，使得当在电源电压上呈现噪声时，当从低电平变为高电平时，可以防止上电复位信号从高电平变为低电平。

8. 发明授权

US08431437B2 Packaging method involving rearrangement of dice 有权
公开(公告)号：US08431437B2
公开(公告)日：2013-04-30
申请号：US13082096
申请日：2011-04-07
申请人： Yu-Ren Chen , Geng-Shin Shen , Tz-Cheng Chiu
发明人： Yu-Ren Chen , Geng-Shin Shen , Tz-Cheng Chiu
IPC分类号： H01L21/56
CPC分类号： H01L21/561 , H01L21/568 , H01L23/3107 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/92 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10158 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2224/96 , H01L2224/82 , H01L2924/00
摘要： A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice and a molding apparatus is used on the substrate to force the polymer material to substantially fill around the plurality of dice. The molding apparatus is removed to expose a surface of the polymer material and a plurality of cutting streets is formed on an exposed surface of the polymer material. The substrate is removed to expose the active surface of the plurality of dice.

9. 发明申请

US20110163426A1 Dice Rearrangement Package Structure Using Layout Process to Form a Compliant Configuration 审中-公开
标题翻译：骰子重排包装结构使用布局流程来形成一个兼容的配置
公开(公告)号：US20110163426A1
公开(公告)日：2011-07-07
申请号：US13048259
申请日：2011-03-15
申请人： GENG-SHIN SHEN , Yu-Ren Chen
发明人： GENG-SHIN SHEN , Yu-Ren Chen
IPC分类号： H01L23/495
CPC分类号： H01L25/50 , H01L21/568 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/25 , H01L24/96 , H01L24/97 , H01L25/0655 , H01L33/486 , H01L33/54 , H01L2221/68359 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/24137 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/0102 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/01094 , H01L2924/014 , H01L2924/09701 , H01L2924/12041 , H01L2924/15311 , H01L2924/3511 , H01L2933/005 , H01L2933/0066 , H01L2224/82 , H01L2924/00
摘要： A dice rearrangement package structure is provided, which a dice having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover the dices and the plurality of pads being exposed; one ends of plurality of metal traces is electrically connected to the each pads; a protection layer is provided to cover the active surface and the other ends of the exposed metal traces is electrically connected to the plurality of conductive elements, the characteristic in that the package body is a B-stage material.
摘要翻译：提供了具有活性表面和底表面的骰子，并且多个衬垫设置在活性表面上的骰子重排包装结构，提供包装体以覆盖所述骰子并且所述多个垫被暴露; 多个金属迹线的一端电连接到每个焊盘; 提供保护层以覆盖有源表面，并且暴露的金属迹线的另一端电连接到多个导电元件，其特征在于封装体是B级材料。

10. 发明授权

US07927922B2 Dice rearrangement package structure using layout process to form a compliant configuration 有权
标题翻译：骰子重排包装结构使用布局流程形成兼容配置
公开(公告)号：US07927922B2
公开(公告)日：2011-04-19
申请号：US12191382
申请日：2008-08-14
申请人： Geng-Shin Shen , Yu-Ren Chen
发明人： Geng-Shin Shen , Yu-Ren Chen
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L25/50 , H01L21/568 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/25 , H01L24/96 , H01L24/97 , H01L25/0655 , H01L33/486 , H01L33/54 , H01L2221/68359 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/24137 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/0102 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/01094 , H01L2924/014 , H01L2924/09701 , H01L2924/12041 , H01L2924/15311 , H01L2924/3511 , H01L2933/005 , H01L2933/0066 , H01L2224/82 , H01L2924/00
摘要： A dice rearrangement package structure is provided, which a dice having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover the dices and the plurality of pads being exposed; one ends of plurality of metal traces is electrically connected to the each pads; a protection layer is provided to cover the active surface and the other ends of the exposed metal traces is electrically connected to the plurality of conductive elements, the characteristic in that the package body is a B-stage material.
摘要翻译：提供了具有活性表面和底表面的骰子，并且多个衬垫设置在活性表面上的骰子重排包装结构，提供包装体以覆盖所述骰子并且所述多个垫被暴露; 多个金属迹线的一端电连接到每个焊盘; 提供保护层以覆盖有源表面，并且暴露的金属迹线的另一端电连接到多个导电元件，其特征在于封装体是B级材料。

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