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1. 发明授权

US08125263B2 Charge pump 有权
标题翻译：电荷泵
公开(公告)号：US08125263B2
公开(公告)日：2012-02-28
申请号：US12827111
申请日：2010-06-30
申请人： Chun-Yi Wu , Wei-Chih Hsieh , Ming-Hung Chang , Wei Hwang
发明人： Chun-Yi Wu , Wei-Chih Hsieh , Ming-Hung Chang , Wei Hwang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/073 , H02M2003/077
摘要： A charge pump is disclosed for amplifying an input voltage received at an input end and outputting the amplified voltage at an output end as an output voltage. The charge pump includes a plurality of source/drain coupling transistors for serving as charging capacitors, and a plurality of cascode-connected transistors being symmetrically connected to between the input end and the output end. The charge pump further includes a plurality of diode-connected transistors to protect the source/drain coupling transistors against breakdown during the course of charge transfer and to speed up the charge transfer.
摘要翻译：公开了一种用于放大在输入端接收的输入电压并将输出端的放大电压作为输出电压输出的电荷泵。电荷泵包括用作充电电容器的多个源极/漏极耦合晶体管，并且多个共源共栅连接晶体管对称地连接到输入端和输出端之间。电荷泵还包括多个二极管连接的晶体管，以在电荷转移过程中保护源极/漏极耦合晶体管免受击穿并且加速电荷转移。

2. 发明授权

US08258741B2 Solar power management system 有权
标题翻译：太阳能发电管理系统
公开(公告)号：US08258741B2
公开(公告)日：2012-09-04
申请号：US12832079
申请日：2010-07-08
申请人： Chun-Yi Wu , Wei-Chih Hsieh , Wei Hwang
发明人： Chun-Yi Wu , Wei-Chih Hsieh , Wei Hwang
IPC分类号： H01M10/46
CPC分类号： H02J7/35 , H02M3/07 , Y02E10/566 , Y02E10/58 , Y10T307/707
摘要： A solar power management system is provided for managing electric energy conversion by a photovoltaic cell module, supplying the converted electric energy to an external load, and storing the converted electric energy in a battery. The solar power management system comprises a multiphase maximum power tracking (MPT) module, a charging circuit, and a voltage conversion module. The multiphase MPT module regulates output current of the photovoltaic cell module to output maximum power within the high limit thereof and obtain improved solar energy conversion efficiency. The voltage conversion module converts the electric energy generated by the photovoltaic cell module into different voltage formats, such as 5.6V DC, 1.0V DC, 0.6˜0.3V DC low voltage, or −1.2V DC negative voltage, to meet different external load requirements. The solar power management system has simple circuitry and can be configured as a system on chip (SoC) at reduced cost while provides very wide applications.
摘要翻译：提供了一种太阳能发电管理系统，用于通过光伏电池模块管理电能转换，将转换的电能提供给外部负载，并将转换的电能存储在电池中。太阳能发电管理系统包括多相最大功率跟踪（MPT）模块，充电电路和电压转换模块。多相MPT模块调节光伏电池模块的输出电流，以在其上限内输出最大功率，并获得改进的太阳能转换效率。电压转换模块将光伏电池模块产生的电能转换成不同的电压格式，如5.6V DC，1.0V DC，0.6〜0.3V直流低电压或-1.2V直流负电压，以满足不同的外部负载要求。太阳能发电管理系统具有简单的电路，可以以低成本配置为片上系统（SoC），同时提供非常广泛的应用。

3. 发明授权

US08419274B2 Fully-on-chip temperature, process, and voltage sensor system 有权
标题翻译：全面的温度，过程和电压传感器系统
公开(公告)号：US08419274B2
公开(公告)日：2013-04-16
申请号：US12910199
申请日：2010-10-22
申请人： Shi-Wen Chen , Ming-Hung Chang , Wei-Chih Hsieh , Wei Hwang
发明人： Shi-Wen Chen , Ming-Hung Chang , Wei-Chih Hsieh , Wei Hwang
IPC分类号： G01K7/00
CPC分类号： G01K7/01 , G01K2219/00
摘要： A fully on-chip temperature, process, and voltage sensor includes a voltage sensor, a process sensor and a temperature sensor. The temperature sensor includes a bias current generator, a ring oscillator, a fixed pulse generator, an AND gate, and a first counter. The bias current generator generates an output current related to temperature according to the operating voltage of chip. The ring oscillator generates an oscillation signal according to the output current. The fixed pulse generator generates a fixed pulse signal. The AND gate is connected to the ring oscillator and the fixed pulse generator for performing a logic AND operation on the oscillation signal and the fixed pulse signal, and generating a temperature sensor signal.
摘要翻译：完全片上的温度，过程和电压传感器包括电压传感器，过程传感器和温度传感器。温度传感器包括偏置电流发生器，环形振荡器，固定脉冲发生器，与门和第一计数器。偏置电流发生器根据芯片的工作电压产生与温度相关的输出电流。环形振荡器根据输出电流产生振荡信号。固定脉冲发生器产生固定的脉冲信号。与门连接到环形振荡器和固定脉冲发生器，用于对振荡信号和固定脉冲信号进行逻辑与运算，并产生温度传感器信号。

4. 发明授权

US09142630B2 Device performance enhancement 有权
标题翻译：设备性能提升
公开(公告)号：US09142630B2
公开(公告)日：2015-09-22
申请号：US13557479
申请日：2012-07-25
申请人： Chang-Yu Wu , Chih-Chiang Chang , Shang-Chih Hsieh , Wei-Chih Hsieh
发明人： Chang-Yu Wu , Chih-Chiang Chang , Shang-Chih Hsieh , Wei-Chih Hsieh
IPC分类号： H01L21/28 , H01L29/423 , H01L29/78
CPC分类号： H01L29/4238 , H01L21/28123 , H01L29/78
摘要： Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.
摘要翻译：除此之外，本文提供了用于增强器件（例如，晶体管）性能的一种或多种技术。在一个实施例中，通过在器件的区域的边缘处形成延伸的虚拟区域并在该区域的非边缘处形成有源区域来增强器件性能。与非边缘区域相比，扩展虚拟区域中存在与半导体制造处理相关的限制。因此，通过将栅极连接到有源区域来形成表现出增强的性能的器件，其中有源区域具有期望的形状，因为它包括在该区域的非边缘内。例如，由于与半导体制造处理相关的限制，可以形成虚拟设备（例如，可能较不响应的）以包括扩展的虚拟区域，其中扩展的虚拟区域具有小于期望的轮廓。

5. 发明申请

US20140027821A1 DEVICE PERFORMANCE ENHANCEMENT 有权
标题翻译：设备性能提升
公开(公告)号：US20140027821A1
公开(公告)日：2014-01-30
申请号：US13557479
申请日：2012-07-25
申请人： Chang-Yu Wu , Chih-Chiang Chang , Shang-Chih Hsieh , Wei-Chih Hsieh
发明人： Chang-Yu Wu , Chih-Chiang Chang , Shang-Chih Hsieh , Wei-Chih Hsieh
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/4238 , H01L21/28123 , H01L29/78
摘要： Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.
摘要翻译：除此之外，本文提供了用于增强器件（例如，晶体管）性能的一种或多种技术。在一个实施例中，通过在器件的区域的边缘处形成延伸的虚拟区域并在该区域的非边缘处形成有源区域来增强器件性能。与非边缘区域相比，扩展虚拟区域中存在与半导体制造处理相关的限制。因此，通过将栅极连接到有源区域来形成表现出增强的性能的器件，其中有源区域具有期望的形状，因为它被包括在该区域的非边缘内。例如，由于与半导体制造处理相关的限制，可以形成虚拟设备（例如，可能较不响应的）以包括扩展的虚拟区域，其中扩展的虚拟区域具有小于期望的轮廓。

6. 发明授权

US08514000B1 Meta-hardened flip-flop 有权
标题翻译：元硬化触发器
公开(公告)号：US08514000B1
公开(公告)日：2013-08-20
申请号：US13562539
申请日：2012-07-31
申请人： Wei-Chih Hsieh , Shang-Chih Hsieh , Chih-Chiang Chang
发明人： Wei-Chih Hsieh , Shang-Chih Hsieh , Chih-Chiang Chang
IPC分类号： H03K3/00
CPC分类号： H03K3/0375 , H03K3/356156
摘要： Some embodiments relate to a flip-flop having a data input terminal, a data output terminal and a clock terminal. The flip-flop includes a master latch, a slave latch, and an isolation element coupled between the master latch output and slave latch. The isolation element is arranged to isolate capacitive loading seen by the output of the master latch that comes from the slave latch. In some embodiments, the master latch includes one or more drive enhancement elements on its feedforward and feedback paths. The slave latch can also include one or more drive enhancement elements on its feedforward and feedback paths. These drive enhancement elements, particularly in combination with the isolation element, may help to reduce the setup and hold times and enhance meta-stability resistance of the flip-flop relative to conventional implementations. Other embodiments are also disclosed.
摘要翻译：一些实施例涉及具有数据输入端，数据输出端和时钟端的触发器。触发器包括主锁存器，从锁存器和耦合在主锁存器输出和从锁存器之间的隔离元件。隔离元件被布置成隔离来自从锁存器的主锁存器的输出所看到的电容性负载。在一些实施例中，主锁存器在其前馈和反馈路径上包括一个或多个驱动增强元件。从锁存器还可以在其前馈和反馈路径上包括一个或多个驱动增强元件。这些驱动增强元件，特别是与隔离元件组合，可以有助于减小建立和保持时间，并且增强触发器相对于传统实现方式的元稳定性。还公开了其他实施例。

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