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1. 发明授权

US06719885B2 Method of reducing stress induced defects in an HDP-CVD process 失效
标题翻译：降低HDP-CVD工艺中应力诱发缺陷的方法
公开(公告)号：US06719885B2
公开(公告)日：2004-04-13
申请号：US10087344
申请日：2002-03-01
申请人： Chun-Sheng Lin , Jui-Hei Huang , Chi-Sheng Lo , Long-Siang Chuang
发明人： Chun-Sheng Lin , Jui-Hei Huang , Chi-Sheng Lo , Long-Siang Chuang
IPC分类号： C23C1434
CPC分类号： H01L21/02164 , C23C16/045 , C23C16/46 , C23C16/50 , H01L21/02274 , H01L21/31612
摘要： A method of reducing stress induced defects in a substrate according to an HDP-CVD process including providing a substrate for depositing a layer of material according to an HDP-CVD process; igniting a plasma for carrying out an HDP-CVD process; adjusting plasma operating parameters to achieve a first deposition-sputter ratio with respect to the substrate; depositing a first portion of the layer of material according to a first range of substrate temperatures; and, depositing at least a second portion of the layer of material according to at least a second range of substrate temperatures.
摘要翻译：根据HDP-CVD工艺减少衬底中的应力诱发缺陷的方法，包括提供用于根据HDP-CVD工艺沉积材料层的衬底; 点燃等离子体进行HDP-CVD工艺; 调节等离子体操作参数以实现相对于基板的第一沉积溅射比; 根据衬底温度的第一范围沉积材料层的第一部分; 以及根据至少第二衬底温度范围沉积材料层的至少第二部分。

2. 发明授权

US08404561B2 Method for fabricating an isolation structure 有权
标题翻译：隔离结构的制造方法
公开(公告)号：US08404561B2
公开(公告)日：2013-03-26
申请号：US12774219
申请日：2010-05-05
申请人： Tze-Liang Lee , Pei-Ren Jeng , Chu-Yun Fu , Chyi Shyuan Chern , Jui-Hei Huang , Chih-Tang Peng , Hao-Ming Lien
发明人： Tze-Liang Lee , Pei-Ren Jeng , Chu-Yun Fu , Chyi Shyuan Chern , Jui-Hei Huang , Chih-Tang Peng , Hao-Ming Lien
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/76232
摘要： The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.
摘要翻译：本发明涉及集成电路制造，更具体地说涉及具有几乎没有空隙的隔离结构的电子器件。一种用于制造隔离结构的示例性方法，包括：提供衬底; 在衬底中形成沟槽; 用第一氧化硅部分地填充沟槽; 将第一氧化硅的表面暴露于包含NH 3和含氟化合物的蒸汽混合物中; 将基板加热至100℃至200℃的温度; 并用第二氧化硅填充沟槽，由此所制成的隔离结构几乎没有空隙。

3. 发明授权

US08580653B2 Method for fabricating an isolation structure 有权
标题翻译：隔离结构的制造方法
公开(公告)号：US08580653B2
公开(公告)日：2013-11-12
申请号：US13775907
申请日：2013-02-25
申请人： Tze-Liang Lee , Pei-Ren Jeng , Chu-Yun Fu , Chyi Shyuan Chern , Jui-Hei Huang , Chih-Tang Peng , Hao-Ming Lien
发明人： Tze-Liang Lee , Pei-Ren Jeng , Chu-Yun Fu , Chyi Shyuan Chern , Jui-Hei Huang , Chih-Tang Peng , Hao-Ming Lien
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/76232
摘要： A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.
摘要翻译：一种制造隔离结构的方法，包括在衬底的顶表面中形成沟槽并用第一氧化物部分地填充沟槽，其中第一氧化物是纯氧化物。部分地填充沟槽包括在沟槽中形成衬层，并且在低于10毫托（mTorr）的压力和约500℃至约1000℃的温度下使用硅烷和氧前体在衬层上形成第一氧化物该方法还包括在第一氧化物的顶部产生固体反应产物。该方法还包括通过在室内在100℃至200℃的温度下加热基底来升华固体反应产物，并通过使载气流过基底而除去升华的固体反应产物。该方法还包括用第二氧化物填充沟槽。

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