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1. 发明授权

US08648401B2 Domain wall assisted spin torque transfer magnetresistive random access memory structure 有权
标题翻译：域壁辅助自旋转矩传递磁阻随机存取存储器结构
公开(公告)号：US08648401B2
公开(公告)日：2014-02-11
申请号：US12884351
申请日：2010-09-17
申请人： Chih-Huang Lai , Sheng-Huang Huang , Kuo-Feng Huang , Ming-Te Liu , Chun-Jung Lin , Ya-Chen Kao , Wen-Cheng Chen
发明人： Chih-Huang Lai , Sheng-Huang Huang , Kuo-Feng Huang , Ming-Te Liu , Chun-Jung Lin , Ya-Chen Kao , Wen-Cheng Chen
IPC分类号： H01L21/02
CPC分类号： H01L43/12 , G11C11/161 , G11C11/1657 , G11C11/1675 , G11C19/0808 , H01L27/228 , H01L43/08
摘要： A semiconductor memory device includes a first ferromagnetic layer magnetically pinned and positioned within a first region of a substrate; a second ferromagnetic layer approximate the first ferromagnetic layer; and a barrier layer interposed between the first ferromagnetic layer and the first portion of the second ferromagnetic layer. The second ferromagnetic layer includes a first portion being magnetically free and positioned within the first region; a second portion magnetically pinned to a first direction and positioned within a second region of the substrate, the second region contacting the first region from a first side; and a third portion magnetically pinned to a second direction and positioned within a third region of the substrate, the third region contacting the first region from a second side.
摘要翻译：半导体存储器件包括磁性固定并位于衬底的第一区域内的第一铁磁层; 第二铁磁层近似第一铁磁层; 以及介于所述第一铁磁层与所述第二铁磁层的所述第一部分之间的阻挡层。第二铁磁层包括无磁性的第一部分，并且位于第一区域内; 第二部分，磁性地固定在第一方向上并且位于所述基板的第二区域内，所述第二区域从第一侧接触所述第一区域; 以及第三部分，其磁性地固定到第二方向并且位于所述基板的第三区域内，所述第三区域从所述第二侧面接触所述第一区域。

2. 发明授权

US08629518B2 Sacrifice layer structure and method for magnetic tunnel junction (MTJ) etching process 有权
标题翻译：牺牲层结构和磁隧道结（MTJ）蚀刻工艺
公开(公告)号：US08629518B2
公开(公告)日：2014-01-14
申请号：US12828593
申请日：2010-07-01
申请人： Yu-Jen Wang , Ya-Chen Kao , Chun-Jung Lin
发明人： Yu-Jen Wang , Ya-Chen Kao , Chun-Jung Lin
IPC分类号： H01L29/82
CPC分类号： H01L43/12 , H01L43/08
摘要： A magnetic tunnel junction (MTJ) etching process uses a sacrifice layer. An MTJ cell structure includes an MTJ stack with a first magnetic layer, a second magnetic layer, and a tunnel barrier layer in between the first magnetic layer and the second magnetic layer, and a sacrifice layer adjacent to the second magnetic layer, where the sacrifice layer protects the second magnetic layer in the MTJ stack from oxidation during an ashing process. The sacrifice layer does not increase a resistance of the MTJ stack. The sacrifice layer can be made of Mg, Cr, V, Mn, Ti, Zr, Zn, or any alloy combination thereof, or any other suitable material. The sacrifice layer can be multi-layered and/or have a thickness ranging from 5 Å to 400 Å. The MTJ cell structure can have a top conducting layer over the sacrifice layer.
摘要翻译：磁隧道结（MTJ）蚀刻工艺使用牺牲层。 MTJ单元结构包括在第一磁性层和第二磁性层之间的具有第一磁性层，第二磁性层和隧道势垒层的MTJ堆叠以及与第二磁性层相邻的牺牲层，其中牺牲层在灰化过程中保护MTJ堆叠中的第二磁性层免受氧化。牺牲层不会增加MTJ堆叠的电阻。牺牲层可以由Mg，Cr，V，Mn，Ti，Zr，Zn或其任何合金组合或任何其它合适的材料制成。牺牲层可以是多层的和/或具有从5到400的厚度。 MTJ单元结构可以在牺牲层上方具有顶部导电层。

3. 发明授权

US08493776B1 MRAM with current-based self-referenced read operations 有权
标题翻译： MRAM具有基于当前的自引用读操作
公开(公告)号：US08493776B1
公开(公告)日：2013-07-23
申请号：US13364756
申请日：2012-02-02
申请人： Hung-Chang Yu , Kai-Chun Lin , Yu-Der Chih , Chun-Jung Lin
发明人： Hung-Chang Yu , Kai-Chun Lin , Yu-Der Chih , Chun-Jung Lin
IPC分类号： G11C11/00
CPC分类号： G11C11/1673 , G11C13/004 , G11C29/74
摘要： A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element.
摘要翻译：磁阻存储器将逻辑值存储在磁性隧道结元件的高电阻和低电阻状态中。代替将元件的电阻与固定阈值进行比较以辨别逻辑状态，元件的电阻在施加低电阻状态之前和之后自我比较。例如，通过将电容器充电到施加读取电流偏压时产生的电压来存储元件在其未知电阻状态下的电阻的量度。然后将元件写入其低电阻状态，并再次施加读取电流偏压以产生表示低电阻状态的另一电压。使用电流求和和提供最小差容差的偏移的比较电路确定元件的电阻是改变还是保持相同。这决定了元素的逻辑状态。

4. 发明申请

US20130038418A1 CONTACTLESS COMMUNICATIONS USING FERROMAGNETIC MATERIAL 有权
标题翻译：使用纤维材料的无缝通信
公开(公告)号：US20130038418A1
公开(公告)日：2013-02-14
申请号：US13206584
申请日：2011-08-10
申请人： Ping-Lin Yang , Jun-De Jin , Fu-Lung Hsueh , Sa-Lly Liu , Tong-Chern Ong , Chun-Jung Lin , Ya-Chen Kao
发明人： Ping-Lin Yang , Jun-De Jin , Fu-Lung Hsueh , Sa-Lly Liu , Tong-Chern Ong , Chun-Jung Lin , Ya-Chen Kao
IPC分类号： H01F38/14 , H01F41/00
CPC分类号： H01L25/0657 , H01F5/00 , H01F27/2804 , H01F41/046 , H01F2027/2809 , H01L23/48 , H01L23/5227 , H01L2225/06531 , H01L2924/0002 , Y10T29/4902 , H01L2924/00
摘要： A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.
摘要翻译：通信结构包括具有第一线圈的第一半导体衬底和在第一半导体衬底上方具有第二线圈的第二半导体衬底。第一和第二线圈的内边缘限定在第一线圈下方延伸并在第二线圈之上的体积的边界。铁磁芯至少部分地位于边界内，使得在第一和第二线圈之间提供互感以在第一和第二线圈之间无线地传输信号或电力。

5. 发明申请

US20120281464A1 Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate 有权
标题翻译：使用字线过驱动和高k金属栅极提高磁隧道接头的编程电流
公开(公告)号：US20120281464A1
公开(公告)日：2012-11-08
申请号：US13550262
申请日：2012-07-16
申请人： Shine Chung , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang , Hung-Sen Wang
发明人： Shine Chung , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang , Hung-Sen Wang
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C8/08 , G11C11/1657 , G11C11/1659
摘要： A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.
摘要翻译：操作磁阻随机存取存储器（MRAM）单元的方法包括提供包括磁隧道结（MTJ）装置的MRAM单元; 以及选择器，包括串联耦合到MTJ器件的源极 - 漏极路径。该方法还包括将过驱动电压施加到选择器的门以接通选择器。

6. 发明申请

US20120127788A1 MRAM Cells and Circuit for Programming the Same 有权
标题翻译： MRAM单元及其编程电路
公开(公告)号：US20120127788A1
公开(公告)日：2012-05-24
申请号：US13364955
申请日：2012-02-02
申请人： Shine Chung , Hung-Sen Wang , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang
发明人： Shine Chung , Hung-Sen Wang , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang
IPC分类号： G11C11/16
CPC分类号： G11C11/1677 , G11C11/1675
摘要： A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured to provide a first writing pulse to write a value into the MRAM cell, and a read circuit configured to measure a status of the MRAM cell. The control circuit is further configured to verify whether a successful writing is achieved through the first writing pulse.
摘要翻译：电路包括磁阻随机存取存储器（MRAM）单元和控制电路。控制电路电耦合到MRAM单元，并且包括被配置为提供第一写入脉冲以将值写入MRAM单元的电流源和被配置为测量MRAM单元的状态的读取电路。控制电路还被配置为验证通过第一写入脉冲是否实现了成功写入。

7. 发明申请

US20100254181A1 Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate 有权
标题翻译：使用字线过驱动和高k金属栅极提高磁隧道接头的编程电流
公开(公告)号：US20100254181A1
公开(公告)日：2010-10-07
申请号：US12687747
申请日：2010-01-14
申请人： Shine Chung , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang , Hung-Sen Wang
发明人： Shine Chung , Tao-Wen Chung , Chun-Jung Lin , Yu-Jen Wang , Hung-Sen Wang
IPC分类号： G11C11/00 , G11C11/14 , G11C5/14
CPC分类号： G11C11/16 , G11C8/08 , G11C11/1657 , G11C11/1659
摘要： A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.
摘要翻译：操作磁阻随机存取存储器（MRAM）单元的方法包括提供包括磁隧道结（MTJ）装置的MRAM单元; 以及选择器，包括串联耦合到MTJ器件的源极 - 漏极路径。该方法还包括将过驱动电压施加到选择器的门以接通选择器。

8. 发明申请

US20090033473A1 Piezoelectric buzzer 失效
标题翻译：压电式蜂鸣器
公开(公告)号：US20090033473A1
公开(公告)日：2009-02-05
申请号：US11882413
申请日：2007-08-01
申请人： Cheng-Sheng Yu , Huey-Lin Hsieh , Tsai-Kun Huang , Jyh-Jang Wey , Wu-Song Chuang , Chun-Jung Lin
发明人： Cheng-Sheng Yu , Huey-Lin Hsieh , Tsai-Kun Huang , Jyh-Jang Wey , Wu-Song Chuang , Chun-Jung Lin
IPC分类号： G08B3/10
CPC分类号： G10K9/122 , G10K9/22
摘要： A piezoelectric buzzer includes a housing unit, a buzzer unit, and first and second terminals. The housing unit includes first and second housings coupled together. The second housing includes a base plate and a pair of spaced apart insert seats, each of which protrudes inwardly from the base plate toward the first housing and is formed with an insert hole. The buzzer unit is disposed in the resonant chamber and includes a vibrating plate and a piezoelectric plate attached to the vibrating plate. The first and second terminals are inserted respectively into the insert holes of the insert seats, and have a respective connection section extending outwardly of the housing unit, and a respective extending section abutting against a respective one of the vibrating plate and the piezoelectric plate.
摘要翻译：压电蜂鸣器包括壳体单元，蜂鸣器单元以及第一和第二端子。壳体单元包括联接在一起的第一和第二壳体。第二壳体包括基板和一对间隔开的插入座，每个插入座从基板朝向第一壳体向内突出并形成有插入孔。蜂鸣器单元设置在谐振室中，并且包括振动板和附接到振动板的压电板。第一和第二端子分别插入到插入座的插入孔中，并且具有从壳体单元向外延伸的相应的连接部分以及抵靠振动板和压电板中的相应一个的相应的延伸部分。

9. 发明授权

US06599680B2 Method for forming cells array of mask read only memory 有权
公开(公告)号：US06599680B2
公开(公告)日：2003-07-29
申请号：US09811392
申请日：2001-03-20
申请人： Chun-Jung Lin
发明人： Chun-Jung Lin
IPC分类号： G03F700
CPC分类号： H01L27/11253 , H01L27/112
摘要： A method for forming cells array of mask read only memory, at least includes: form numerous gate structures on substrate; form numerous doped regions in uncovered part of substrate; form first conductor layer on uncovered part of substrate with a thickness essentially equal to thickness of gate structures; form first dielectric layer on first conductor layer; form second conductor layer on both gate structures and first dielectric layer; perform a pattern transform process for transferring both second conductor layer and gate structures into conductor lines as word lines; form second dielectric layer on sidewalls of conductor lines to form spacer; form code photoresist on second conductor layer; and perform ions implantation process for implant numerous ions into partial substrate which is not covered by code photoresist.

10. 发明授权

US06570235B2 Cells array of mask read only memory 有权
标题翻译：单元阵列的掩码只读内存
公开(公告)号：US06570235B2
公开(公告)日：2003-05-27
申请号：US09811393
申请日：2001-03-20
申请人： Chun-Jung Lin
发明人： Chun-Jung Lin
IPC分类号： H01L2976
CPC分类号： H01L27/11253 , G11C17/12 , H01L27/112
摘要： A cells array of mask read only memory, at least includes numerous essentially parallel cells chains and numerous isolation dielectric layers which are located between any two adjacent cells chains. Each cells chain at least includes: numerous gates that located on a substrate, numerous doped regions, numerous polysilicon layers, numerous cover dielectric layers, a conductor layer and numerous isolation dielectric layers. Whereby, each gate at least include a gate dielectric layer, a gate conductor layer and a spacer, and height of spacer is larger than summation of thickness of gate dielectric layer and thickness of gate conductor layer; doped regions are located in the substrate, and each doped region is located between two neighboring gates; each doped region is covered by one polysilicon layer, and height of each polysilicon layer is larger than summation of thickness of gate dielectric layer and thickness of each gate conductor layer; each polysilicon layer is covered by one cover dielectric layer; and conductor layer covers both the gates and the cover dielectric layers. Moreover, height of each isolation dielectric layer is larger than summation of thickness of gate dielectric layer and thickness of each gate conductor layer.
摘要翻译：掩模只读存储器的单元阵列至少包括许多基本上平行的细胞链和位于任何两个相邻细胞链之间的许多隔离介电层。每个细胞链至少包括：位于衬底上的多个栅极，多个掺杂区域，多个多晶硅层，多个覆盖电介质层，导体层和许多隔离电介质层。由此，每个栅极至少包括栅极介电层，栅极导体层和间隔物，并且间隔物的高度大于栅极介电层的厚度和栅极导体层的厚度的总和; 掺杂区域位于衬底中，并且每个掺杂区域位于两个相邻栅极之间; 每个掺杂区域被一个多晶硅层覆盖，并且每个多晶硅层的高度大于栅极介电层的厚度和每个栅极导体层的厚度的总和; 每个多晶硅层被一个覆盖电介质层覆盖; 并且导体层覆盖栅极和覆盖电介质层。此外，每个隔离电介质层的高度大于栅极介电层的厚度和每个栅极导体层的厚度的总和。

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