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1. 发明授权

US06396753B1 Method and structure for testing embedded flash memory 有权
标题翻译：嵌入式闪存测试方法和结构
公开(公告)号：US06396753B1
公开(公告)日：2002-05-28
申请号：US09826497
申请日：2001-04-05
申请人： Chun-Hsiung Hung , Nai-Ping Kuo , Tu-Shun Chen , Ho-Chun Liou
发明人： Chun-Hsiung Hung , Nai-Ping Kuo , Tu-Shun Chen , Ho-Chun Liou
IPC分类号： G11C700
CPC分类号： G11C29/50 , G11C16/04 , G11C2207/104
摘要： A method and structure for testing embedded flash memory including a memory array and a logic element. A control transistor is disposed and is connected between a sense amplifier and an I/O buffer in the memory array, and a speed control pin connected to the logic element in one terminal is coupled to the gate terminal of the control transistor in the other terminal to switch the control transistor on or off. Turning off the control transistor after a test time by the speed control pin closes the channel between the sense amplifier and I/O buffer, and an output signal from the memory array to a test system connected to the logic element is detected with the test system to determine an access time of the memory array.
摘要翻译：一种用于测试包括存储器阵列和逻辑元件的嵌入式闪速存储器的方法和结构。控制晶体管被设置并连接在存储器阵列中的读出放大器和I / O缓冲器之间，并且连接到一个端子中的逻辑元件的速度控制引脚耦合到另一个端子中的控制晶体管的栅极端子开关控制晶体管。通过速度控制引脚在测试时间后关闭控制晶体管，关闭读出放大器和I / O缓冲器之间的通道，并从测试系统检测到从存储器阵列到连接到逻辑元件的测试系统的输出信号以确定存储器阵列的访问时间。

2. 发明授权

US06845052B1 Dual reference cell sensing scheme for non-volatile memory 有权
标题翻译：用于非易失性存储器的双参考单元感测方案
公开(公告)号：US06845052B1
公开(公告)日：2005-01-18
申请号：US10250040
申请日：2003-05-30
申请人： Hsin-Yi Ho , Nai-Ping Kuo , Chun-Hsiung Hung , Gin-Liang Chen , Wen-Chiao Ho , Ho-Chun Liou
发明人： Hsin-Yi Ho , Nai-Ping Kuo , Chun-Hsiung Hung , Gin-Liang Chen , Wen-Chiao Ho , Ho-Chun Liou
IPC分类号： G11C7/06 , G11C7/14 , G11C16/28 , G11C7/02
CPC分类号： G11C7/14 , G11C7/062 , G11C16/28 , G11C2207/2227
摘要： The present invention provides a dual reference cell sensing scheme for non-volatile memory. A high voltage reference cell and a low voltage reference cell are individually coupled to two sense amplifiers for providing two distinct reference voltages for comparison against the memory cell voltage. The output of the two sense amplifiers is further connected to a second stage sense amplifier to determine the status of the memory. The dual reference cell sensing scheme provides an increased sensing window which increases performance under low voltage application. The dual reference cell sensing scheme can be implemented by either voltage-based, current-based, or ground.
摘要翻译：本发明提供了一种用于非易失性存储器的双参考单元感测方案。高电压参考单元和低电压参考单元分别耦合到两个读出放大器，用于提供用于与存储单元电压进行比较的两个不同的参考电压。两个读出放大器的输出进一步连接到第二级读出放大器以确定存储器的状态。双参考电池感测方案提供增加的感测窗口，其在低电压应用下增加性能。双参考电池感测方案可以通过基于电压，基于电流或接地来实现。

3. 发明授权

US06665216B1 Apparatus and system for reading non-volatile memory with dual reference cells 有权
标题翻译：用于读取具有双参考单元的非易失性存储器的装置和系统
公开(公告)号：US06665216B1
公开(公告)日：2003-12-16
申请号：US10202245
申请日：2002-07-23
申请人： Hsin-Yi Ho , Nai-Ping Kuo , Chun-Hsiung Hung , Gin-Laing Chen , Wen-Chiao Ho , Ho-Chun Liou
发明人： Hsin-Yi Ho , Nai-Ping Kuo , Chun-Hsiung Hung , Gin-Laing Chen , Wen-Chiao Ho , Ho-Chun Liou
IPC分类号： G11C700
CPC分类号： G11C16/28 , G11C7/062
摘要： A system for reading data in a memory cell includes three comparators, each of which has two inputs. A first reference cell having a low reference voltage is coupled to one input of the first comparator. A second reference cell having a high reference voltage is coupled to one input of the second comparator. A memory cell having a memory cell voltage is coupled to the other input of the first and second comparators. One input of the third comparator is coupled to the first comparator's output signal, which includes a difference voltage between the memory cell voltage and the low reference voltage. The other input of the third comparator is coupled to the second comparator's output signal, which includes a difference voltage between the memory cell voltage and the high reference voltage. A method and apparatus for reading data in a memory cell also are described.
摘要翻译：用于读取存储器单元中的数据的系统包括三个比较器，每个比较器具有两个输入。具有低参考电压的第一参考单元耦合到第一比较器的一个输入端。具有高参考电压的第二参考单元耦合到第二比较器的一个输入端。具有存储单元电压的存储单元耦合到第一和第二比较器的另一个输入端。第三比较器的一个输入耦合到第一比较器的输出信号，其包括存储单元电压和低参考电压之间的差电压。第三比较器的另一输入端耦合到第二比较器的输出信号，其包括存储单元电压和高参考电压之间的差电压。还描述了一种用于在存储器单元中读取数据的方法和装置。

4. 发明授权

US06421267B1 Memory array architecture 有权
标题翻译：内存阵列架构
公开(公告)号：US06421267B1
公开(公告)日：2002-07-16
申请号：US09840709
申请日：2001-04-24
申请人： Nai-Ping Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Ho-Chun Liou
发明人： Nai-Ping Kuo , Hsin-Yi Ho , Chun-Hsiung Hung , Ho-Chun Liou
IPC分类号： G11C1134
CPC分类号： G11C16/3495 , G11C16/0483 , G11C16/10 , G11C2216/16
摘要： A memory array architecture includes a plurality of memory cells formed into rows and columns. A plurality of bit lines is connected to the memory cells through select transistors. By disposing adjacent bit lines into different metal layers or alternatively interlocating adjacent bit lines, the coupling effect between bit lines can be effectively reduced, and thus can improve reading speed of memory while performing read operation.
摘要翻译：存储器阵列结构包括形成行和列的多个存储单元。多个位线通过选择晶体管连接到存储单元。通过将相邻的位线布置在不同的金属层中或者可选地相互位置相邻的位线，可以有效地减少位线之间的耦合效应，从而可以在执行读取操作时提高存储器的读取速度。

5. 发明授权

US08717813B2 Method and apparatus for leakage suppression in flash memory in response to external commands 有权
标题翻译：响应于外部命令，闪存中泄漏抑制的方法和装置
公开(公告)号：US08717813B2
公开(公告)日：2014-05-06
申请号：US13308266
申请日：2011-11-30
申请人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
发明人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
IPC分类号： G11C11/34
CPC分类号： G11C16/3409 , G11C11/5635 , G11C16/0483 , G11C16/14
摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.
摘要翻译：本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。该设备还包括用于从存储设备外部的源接收命令的命令接口。该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

6. 发明申请

US20130242665A1 Method and Apparatus for Shortened Erase Operation 有权
标题翻译：用于缩短擦除操作的方法和装置
公开(公告)号：US20130242665A1
公开(公告)日：2013-09-19
申请号：US13536555
申请日：2012-06-28
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo , Chin-Hung Chang , Chang-Ting Chen
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo , Chin-Hung Chang , Chang-Ting Chen
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/14 , G11C29/34 , G11C2029/2602
摘要： A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.
摘要翻译：非易失性存储器阵列具有不同持续时间的多个擦除过程。可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。

7. 发明申请

US20120262988A1 METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY 有权
标题翻译：闪存中泄漏抑制的方法和装置
公开(公告)号：US20120262988A1
公开(公告)日：2012-10-18
申请号：US13308301
申请日：2011-11-30
申请人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
发明人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
IPC分类号： G11C16/10
CPC分类号： G11C16/3409 , G11C11/5635 , G11C16/0483 , G11C16/14
摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block.
摘要翻译：本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。在一个实施例中，描述了一种闪存器件，其包括包括多个存储器单元块的存储器阵列。该装置还包括执行泄漏抑制处理的控制器。泄漏抑制过程包括确定给定的存储单元块包括一个或多个过擦除存储器单元。在确定时，泄漏抑制处理还包括执行软程序操作以增加给定块中的被擦除的存储器单元的阈值电压。

8. 发明授权

US08094493B2 Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control 有权
标题翻译：使用改进的参考细胞修剪算法的存储器件和方法用于精确的读操作窗口控制
公开(公告)号：US08094493B2
公开(公告)日：2012-01-10
申请号：US11271300
申请日：2005-11-10
申请人： Wen-Yi Hsieh , Ken-Hui Chen , Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Ching-Chung Lin , Chuan-Ying Yu
发明人： Wen-Yi Hsieh , Ken-Hui Chen , Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Ching-Chung Lin , Chuan-Ying Yu
IPC分类号： G11C11/34 , G11C7/02
CPC分类号： G11C16/28 , G11C16/04 , G11C16/0475 , G11C29/028 , G11C29/24 , G11C29/50004 , G11C2211/5634
摘要： A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding reference line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).
摘要翻译：公开了一种存储器件，其包括多个字线和以多个模式之一工作并耦合到至少一个字线的多个存储单元。存储装置还包括多个参考线和参考单元。每个参考单元对应于一个操作模式，为相应模式提供参考电流，并耦合到至少一个参考线。来自参考单元的参考单元电流也可以与目标范围进行比较，并且如果在目标范围之外，可以相应地调整相应参考线上的电压电平，使得参考电流落在目标范围内（即，参考当前修剪）。

9. 发明申请

US20110019487A1 APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES 有权
标题翻译：用于检测存储器件中的字线泄漏的装置和方法
公开(公告)号：US20110019487A1
公开(公告)日：2011-01-27
申请号：US12899439
申请日：2010-10-06
申请人： Han-Sung Chen , Su-Chueh Lo , Chun-Hsiung Hung , Nai-Ping Kuo , Ming-Chih Hsieh , Wen-Pin Tsai
发明人： Han-Sung Chen , Su-Chueh Lo , Chun-Hsiung Hung , Nai-Ping Kuo , Ming-Chih Hsieh , Wen-Pin Tsai
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C8/08 , G11C29/025 , G11C2029/1202 , G11C2029/5006
摘要： According to an embodiment of the present invention, a method for detecting word line leakage in a memory device includes coupling a first word line in the memory device to a voltage source while coupling a second word line in the memory device to a ground level voltage. Next, the first word line is decoupled from the voltage source. The method also includes comparing a current of the first word line with a predetermined reference current for determining a leakage condition of the word line.
摘要翻译：根据本发明的实施例，一种用于检测存储器件中的字线泄漏的方法包括将存储器件中的第一字线耦合到电压源，同时将存储器件中的第二字线耦合到地电平电压。接下来，第一个字线与电压源去耦。该方法还包括将第一字线的电流与用于确定字线的泄漏状况的预定参考电流进行比较。

10. 发明授权

US07532513B2 Apparatus and method for detecting word line leakage in memory devices 有权
标题翻译：用于检测存储器件中的字线泄漏的装置和方法
公开(公告)号：US07532513B2
公开(公告)日：2009-05-12
申请号：US11845690
申请日：2007-08-27
申请人： Han-Sung Chen , Su-Chueh Lo , Chun-Hsiung Hung , Nai-Ping Kuo , Ming-Chih Hsieh , Wen-Pin Tsai
发明人： Han-Sung Chen , Su-Chueh Lo , Chun-Hsiung Hung , Nai-Ping Kuo , Ming-Chih Hsieh , Wen-Pin Tsai
IPC分类号： G11C11/34
CPC分类号： G11C29/02 , G11C8/08 , G11C29/025 , G11C2029/1202 , G11C2029/5006
摘要： A method for detecting word line leakage in a memory device includes coupling a first plurality of word lines in the memory device to a voltage source while grounding a second plurality of word lines. Each of the second plurality of word lines is adjacent to a corresponding one of the first plurality of word lines. The method includes waiting for a period of time to allow the word lines to reach a predetermined read voltage level. The method also includes decoupling the first plurality of word lines from the voltage source and waiting for a second predetermined period of time to allow the first plurality of word lines to discharge. The method further includes sensing a current associated with the word lines, and comparing the current with a predetermined reference current which is selected for identifying a word line leakage condition associated with the first plurality of word lines.
摘要翻译：一种用于检测存储器件中的字线泄漏的方法，包括：将所述存储器件中的第一多个字线耦合到电压源，同时接地第二多个字线。第二多个字线中的每一个与第一多个字线中的相应一个字线相邻。该方法包括等待一段时间以允许字线达到预定的读取电压电平。该方法还包括将第一多个字线与电压源去耦，并等待第二预定时间段以允许第一个多个字线放电。该方法还包括感测与字线相关联的电流，以及将电流与为了识别与第一多个字线相关联的字线泄漏状况而被选择的预定参考电流进行比较。

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