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1. 发明授权

US08638636B2 Word line decoder circuit apparatus and method 有权
标题翻译：字线解码电路装置及方法
公开(公告)号：US08638636B2
公开(公告)日：2014-01-28
申请号：US12816960
申请日：2010-06-16
申请人： Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C8/00
CPC分类号： G11C16/16
摘要： One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.
摘要翻译：该技术的一个实施例是一种装置，存储器集成电路。存储器集成电路具有字线地址解码电路。该电路允许选择单个字线以具有擦除电压。解码器电路包括反相器和逻辑。逆变器具有输入和控制字线的输出以执行擦除操作。输入的电压范围在第一参考电压和第二电压基准之间延伸。电压基准的示例是电压源和地。在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。

2. 发明授权

US08374007B2 Supplying power with maintaining its output power signal with the assistance of another power apply and method therefor 有权
标题翻译：在另一种电源的协助下，通过维持其输出功率信号来提供电力及其方法
公开(公告)号：US08374007B2
公开(公告)日：2013-02-12
申请号：US12820422
申请日：2010-06-22
申请人： Chih-Ting Hu , Chun-Hsiung Hung , Chuan-Ying Yu , Wu-Chin Peng , Kuen-Long Chang , Ken-Hui Chen
发明人： Chih-Ting Hu , Chun-Hsiung Hung , Chuan-Ying Yu , Wu-Chin Peng , Kuen-Long Chang , Ken-Hui Chen
IPC分类号： H02M7/25 , H02M7/00
CPC分类号： H02M3/07 , G11C5/145 , H02M2001/0032 , Y02B70/16
摘要： A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing.
摘要翻译：提供电源装置和供电方法。用于具有第一功率信号的系统中的装置包括辅助单元和电源装置。辅助单元选择性地输出根据第一功率信号的至少一个维持信号。电源装置输出第二电力信号，其中电源装置根据至少一个维持信号维持第二电力信号，例如处于非空闲状态，例如空闲或待机状态或其他合适的定时。

3. 发明申请

US20110227552A1 Apparatus of Supplying Power and Method Therefor 有权
标题翻译：供电装置及其方法
公开(公告)号：US20110227552A1
公开(公告)日：2011-09-22
申请号：US12820422
申请日：2010-06-22
申请人： Chih-Ting Hu , Chun-Hsiung Hung , Chuan-Ying Yu , Wu-Chin Peng , Kuen-Long Chang , Ken-Hui Chen
发明人： Chih-Ting Hu , Chun-Hsiung Hung , Chuan-Ying Yu , Wu-Chin Peng , Kuen-Long Chang , Ken-Hui Chen
IPC分类号： G05F3/02
CPC分类号： H02M3/07 , G11C5/145 , H02M2001/0032 , Y02B70/16
摘要： A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing.
摘要翻译：提供电源装置和供电方法。用于具有第一功率信号的系统中的装置包括辅助单元和电源装置。辅助单元选择性地输出根据第一功率信号的至少一个维持信号。电源装置输出第二电力信号，其中电源装置根据至少一个维持信号维持第二电力信号，例如处于非空闲状态，例如空闲或待机状态或其他合适的定时。

4. 发明申请

US20110038218A1 Memory Chip and Method for Operating the Same 有权
标题翻译：内存芯片及其操作方法
公开(公告)号：US20110038218A1
公开(公告)日：2011-02-17
申请号：US12911173
申请日：2010-10-25
申请人： Kuen-Long Chang , Chun-Hsiung Hung , Chuan-Ying Yu , Chun-Yi Lee
发明人： Kuen-Long Chang , Chun-Hsiung Hung , Chuan-Ying Yu , Chun-Yi Lee
IPC分类号： G11C29/08
CPC分类号： G11C29/022 , G11C29/02
摘要： A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.
摘要翻译：提供了一种存储芯片及其操作方法。存储器芯片包括多个焊盘。该方法包括分别将多个第一测试信号输入到焊盘，其中对应于两个物理相邻的焊盘的第一测试信号是互补的; 将多个分别连续到第一测试信号的第二测试信号输入到焊盘，其中对应于每个焊盘的第一测试信号和第二测试信号是互补的; 以及如果所述第一测试信号和所述第二测试信号被所述存储芯片成功接收，则从所述存储器芯片输出预期数据。

5. 发明申请

US20090295419A1 MEMORY CHIP AND METHOD FOR OPERATING THE SAME 有权
标题翻译：存储芯片及其操作方法
公开(公告)号：US20090295419A1
公开(公告)日：2009-12-03
申请号：US12256042
申请日：2008-10-22
申请人： Kuen-Long CHANG , Chun-Hsiung HUNG , Chuan-Ying YU , Chun-Yi LEE
发明人： Kuen-Long CHANG , Chun-Hsiung HUNG , Chuan-Ying YU , Chun-Yi LEE
IPC分类号： G01R31/3187
CPC分类号： G11C29/022 , G11C29/02
摘要： A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.
摘要翻译：提供了一种存储芯片及其操作方法。存储器芯片包括多个焊盘。该方法包括分别将多个第一测试信号输入到焊盘，其中对应于两个物理相邻的焊盘的第一测试信号是互补的; 将多个分别连续到第一测试信号的第二测试信号输入到焊盘，其中对应于每个焊盘的第一测试信号和第二测试信号是互补的; 以及如果所述第一测试信号和所述第二测试信号被所述存储芯片成功接收，则从所述存储器芯片输出预期数据。

6. 发明授权

US07518926B2 Systems and methods for improved programming of flash based devices 有权
标题翻译：用于改进基于闪存的设备编程的系统和方法
公开(公告)号：US07518926B2
公开(公告)日：2009-04-14
申请号：US11777348
申请日：2007-07-13
申请人： Chun-Hsiung Hung , Chuan-Ying Yu
发明人： Chun-Hsiung Hung , Chuan-Ying Yu
IPC分类号： G11C11/34
CPC分类号： G11C16/3468 , G11C16/12 , G11C16/3404
摘要： A flash based device in configured for soft programming to correct for over-erase effect; however, the soft programming current is limited so as not to exceed the current that can be supplied during soft programming. Additionally, the voltage on the source node of each cell on the flash based device is maintained at a non-zero level, in order to allow for the use of a higher word line voltage, but help prevent an over soft programming effect.
摘要翻译：基于闪存的设备，配置为软编程以校正过擦除效应; 然而，软编程电流受到限制，以便不超过软编程期间可以提供的电流。另外，基于闪存的设备上的每个单元的源节点上的电压保持在非零电平，以便允许使用更高的字线电压，但有助于防止过度的软编程效应。

7. 发明授权

US07180782B2 Read source line compensation in a non-volatile memory 有权
标题翻译：在非易失性存储器中读取源极线补偿
公开(公告)号：US07180782B2
公开(公告)日：2007-02-20
申请号：US11151168
申请日：2005-06-10
申请人： Chuan-Ying Yu , Nai-Ping Kuo , Ken-Hui Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chuan-Ying Yu , Nai-Ping Kuo , Ken-Hui Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C16/28
CPC分类号： G11C29/02 , G11C16/04 , G11C29/025 , G11C29/028 , G11C2029/5002
摘要： Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that are shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.
摘要翻译：根据本发明的非易失性存储器电路提供具有通过互连导体线在一组读出放大器之间共享的多个参考单元的参考存储器。每个参考存储器的较高数量的参考单元产生更大量的用于对多个源极线进行充电的电流。多个源极线耦合到互连导体条，用于与耦合到主存储器阵列中的存储器单元的源极线的电容匹配。在硅晶片出来之后，对由主存储器阵列中的源极线产生的电容的测量以及由参考阵列中的源极线产生的电容进行可选的修整。电容匹配的另一校准是通过切割源极线的一部分或者将一部分添加到源极线来修剪耦合到互连导体条和参考存储器的源极线之一来实现的。

8. 发明申请

US20060267059A1 Peripheral circuit architecture for array memory 审中-公开
标题翻译：阵列存储器的外围电路架构
公开(公告)号：US20060267059A1
公开(公告)日：2006-11-30
申请号：US11137098
申请日：2005-05-25
申请人： Chuan-Ying Yu , Chun-Hsiung Hung , Su-Chueh Lo , Nai-Ping Kuo , Ken-Hui Chen
发明人： Chuan-Ying Yu , Chun-Hsiung Hung , Su-Chueh Lo , Nai-Ping Kuo , Ken-Hui Chen
IPC分类号： H01L29/94
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898
摘要： A wordline driver cell, coupled to at least one wordline, includes at least one diffusion region and at least one wordline driver semiconductor switching device formed in the at least one diffusion region. The at least one wordline driver semiconductor switching device has a channel width that is arranged perpendicular to a longitudinal axis of the at least one wordline.
摘要翻译：耦合到至少一个字线的字线驱动器单元包括形成在至少一个扩散区域中的至少一个扩散区域和至少一个字线驱动器半导体开关器件。所述至少一个字线驱动器半导体开关器件具有垂直于所述至少一个字线的纵向轴线布置的沟道宽度。

9. 发明申请

US20060104113A1 Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control 有权
标题翻译：使用改进的参考细胞修剪算法的存储器件和方法用于精确的读操作窗口控制
公开(公告)号：US20060104113A1
公开(公告)日：2006-05-18
申请号：US11271300
申请日：2005-11-10
申请人： Wen-Yi Hsieh , Ken-Hui Chen , Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Ching-Chung Lin , Chuan-Ying Yu
发明人： Wen-Yi Hsieh , Ken-Hui Chen , Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Ching-Chung Lin , Chuan-Ying Yu
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C16/04 , G11C16/0475 , G11C29/028 , G11C29/24 , G11C29/50004 , G11C2211/5634
摘要： A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding referece line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).
摘要翻译：公开了一种存储器件，其包括多个字线和以多个模式之一工作并耦合到至少一个字线的多个存储单元。存储装置还包括多个参考线和参考单元。每个参考单元对应于一个操作模式，为相应模式提供参考电流，并耦合到至少一个参考线。来自参考单元的参考单元电流也可以与目标范围进行比较，并且如果在目标范围之外，可以相应地调整相应参考线上的电压电平，使得参考电流落在目标范围内（即，参考当前修剪）。

10. 发明授权

US09225240B2 Charge pump utilizing external clock signal 有权
标题翻译：电荷泵利用外部时钟信号
公开(公告)号：US09225240B2
公开(公告)日：2015-12-29
申请号：US12786122
申请日：2010-05-24
申请人： Chun-Hsiung Hung , Chuan-Ying Yu
发明人： Chun-Hsiung Hung , Chuan-Ying Yu
IPC分类号： G05F3/02 , G05F1/10 , H02M3/07
CPC分类号： H02M3/073
摘要： A method of generating a pumping voltage in an integrated circuit includes receiving an external clock signal from outside of the integrated circuit. The frequency of the received external clock signal is changed according to one or more modulation ratios, resulting in one or more respective modulated external clock signal. The external clock signal or one of the modulated external clock signals is then selected for use as a pump clock signal. The pump clock signal is used for driving the pump capacitance of a pump circuit for generating the pumping voltage.
摘要翻译：在集成电路中产生泵浦电压的方法包括从集成电路的外部接收外部时钟信号。接收到的外部时钟信号的频率根据一个或多个调制比而改变，导致一个或多个相应调制的外部时钟信号。然后选择外部时钟信号或调制的外部时钟信号之一用作泵浦时钟信号。泵时钟信号用于驱动泵电路的泵电容以产生泵浦电压。

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