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1. 发明授权

US07812638B2 Input output device for mixed-voltage tolerant 有权
标题翻译：输入输出设备，耐混电压
公开(公告)号：US07812638B2
公开(公告)日：2010-10-12
申请号：US12184271
申请日：2008-08-01
申请人： Chua-Chin Wang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
发明人： Chua-Chin Wang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
IPC分类号： H03K19/0185
CPC分类号： H03K19/00315
摘要： An input output device coupled between a core circuit and a pad and including an output cell, an input cell, and a pre-driver. The output cell includes an output stage and a voltage level converter. The output stage includes a first transistor and a second transistor connected to the first transistor in serial between a first supply voltage and a second voltage. The voltage level converter generates a first gate voltage to the first transistor according to the first voltage and a data signal. When the first supply voltage is increased, the first gate voltage is increased. When the data signal is at a high level, the first transistor is turned on. The input cell includes a pull unit and a first N-type transistor. The pre-driver turns off the first and the second transistors.
摘要翻译：耦合在核心电路和焊盘之间并包括输出单元，输入单元和预驱动器的输入输出设备。输出单元包括输出级和电压电平转换器。输出级包括在第一电源电压和第二电压之间串联连接到第一晶体管的第一晶体管和第二晶体管。电压电平转换器根据第一电压和数据信号产生到第一晶体管的第一栅极电压。当第一电源电压增加时，第一栅极电压增加。当数据信号处于高电平时，第一晶体管导通。输入单元包括拉单元和第一N型晶体管。预驱动器关闭第一和第二晶体管。

2. 发明授权

US08212590B2 Mixed-voltage I/O buffer 有权
标题翻译：混合电压I / O缓冲器
公开(公告)号：US08212590B2
公开(公告)日：2012-07-03
申请号：US13067598
申请日：2011-06-13
申请人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang
发明人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang
IPC分类号： H03B1/00
CPC分类号： H03K19/0013 , H03K3/356113 , H03K19/018521
摘要： A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level.
摘要翻译：混合电压I / O缓冲器包括输入缓冲电路。输入缓冲电路包括第一反相器，第一电压电平限制电路，第一电压电平上拉电路，输入级电路和逻辑校准电路。第一反相器反相输入信号以产生第一控制信号。第一电压电平限制电路限制外部信号的电压电平，以产生传输到第一逆变器的输入信号，以防止第一逆变器的电过载。第一电压上拉电路由第一控制信号控制，以提高输入到第一反相器的输入信号的电压电平。输入级电路接收第一控制信号以产生输入到核心电路的相应的数字信号。当由于输入信号具有低电压电平而使第一反相器误操作时，逻辑校准电路校准第一控制信号的电压电平。

3. 发明申请

US20100277216A1 I/O Buffer Circuit 审中-公开
标题翻译： I / O缓冲电路
公开(公告)号：US20100277216A1
公开(公告)日：2010-11-04
申请号：US12835202
申请日：2010-07-13
申请人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
发明人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
IPC分类号： H03L5/00
CPC分类号： H03K19/018521 , H03K19/018528
摘要： An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.
摘要翻译：提供输出缓冲电路。输出缓冲电路从第一核心电路（10）接收控制信号（OE）和数据信号（Dout），并根据控制信号在发送模式下工作。输出缓冲电路根据数据信号逻辑电平和电源电压（VDDIO）将数据信号转换成第一电压电平或接地电压电平的输出信号。电源电压被调整为上拉或下拉输出信号的第一电压电平。

4. 发明授权

US07786760B2 I/O buffer circuit 有权
标题翻译： I / O缓冲电路
公开(公告)号：US07786760B2
公开(公告)日：2010-08-31
申请号：US12193299
申请日：2008-08-18
申请人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
发明人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/018528
摘要： An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.
摘要翻译：提供输出缓冲电路。输出缓冲电路从第一核心电路（10）接收控制信号（OE）和数据信号（Dout），并根据控制信号在发送模式下工作。输出缓冲电路根据数据信号逻辑电平和电源电压（VDDIO）将数据信号转换成第一电压电平或接地电压电平的输出信号。电源电压被调整为上拉或下拉输出信号的第一电压电平。

5. 发明授权

US07986171B2 Mixed-voltage I/O buffer 有权
标题翻译：混合电压I / O缓冲器
公开(公告)号：US07986171B2
公开(公告)日：2011-07-26
申请号：US12289132
申请日：2008-10-21
申请人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang
发明人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang
IPC分类号： H03B1/00
CPC分类号： H03K19/0013 , H03K3/356113 , H03K19/018521
摘要： A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current.
摘要翻译：混合电压输入/输出（I / O）缓冲器包括输出缓冲电路。输出缓冲电路包括输出级电路，栅极跟踪电路和浮动N阱电路。输出级电路包括堆叠上拉P型晶体管和堆叠式下拉式N型晶体管，其中堆叠上拉P型晶体管的第一P型晶体管和第一N型晶体管堆叠的下拉式N型晶体管耦合到I / O焊盘。栅极跟踪电路根据I / O焊盘的电压来控制第一P型晶体管的栅极电压，以防止漏电流。浮动N阱电路为第一P型晶体管的N阱和第二P型晶体管的N阱提供N阱电压，控制栅极的第一P型晶体管的栅极电压跟踪电路，以防止漏电流。

6. 发明授权

US07627371B2 Implantable biomedical chip with modulator for a wireless neural stimulation system 失效
标题翻译：植入式生物医学芯片与无线神经刺激系统的调制器
公开(公告)号：US07627371B2
公开(公告)日：2009-12-01
申请号：US11352331
申请日：2006-02-13
申请人： Chua-Chin Wang , Tzung-Je Lee
发明人： Chua-Chin Wang , Tzung-Je Lee
IPC分类号： A61N1/18
CPC分类号： A61N1/32 , A61N1/36071 , A61N1/3787
摘要： An implantable biomedical chip with modulator for a wireless neural stimulating system. The implantable biomedical chip comprises a power regulator, a demodulator, a baseband circuit, a D/A converter, an instrumentation amplifier, an A/D converter and a modulator. The modulator is mounted on the implantable biomedical chip, and can achieve full-duplex communication to improve the controllability and observability. This also reduces the power consumption and area occupation as compared with using discrete components. Therefore, the integration of the implantable biomedical chip can be easily accomplished.
摘要翻译：一种具有无线神经刺激系统调制器的植入式生物医学芯片。可植入生物医学芯片包括功率调节器，解调器，基带电路，D / A转换器，仪表放大器，A / D转换器和调制器。调制器安装在植入式生物医学芯片上，可实现全双工通信，提高可控性和可观察性。与使用分立元件相比，这也降低了功耗和占用面积。因此，可以容易地实现植入式生物医学芯片的集成。

7. 发明申请

US20090108870A1 I/O BUFFER CIRCUIT 有权
标题翻译： I / O缓冲电路
公开(公告)号：US20090108870A1
公开(公告)日：2009-04-30
申请号：US12193299
申请日：2008-08-18
申请人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
发明人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang , Tie-Yan Chang
IPC分类号： H03K19/0185 , H03L5/00
CPC分类号： H03K19/018521 , H03K19/018528
摘要： An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.
摘要翻译：提供输出缓冲电路。输出缓冲电路从第一核心电路（10）接收控制信号（OE）和数据信号（Dout），并根据控制信号在发送模式下工作。输出缓冲电路根据数据信号逻辑电平和电源电压（VDDIO）将数据信号转换成第一电压电平或接地电压电平的输出信号。电源电压被调整为上拉或下拉输出信号的第一电压电平。

8. 发明申请

US20070191888A1 Implantable biomedical chip with modulator for a wireless neural stimulation system 失效
标题翻译：植入式生物医学芯片与无线神经刺激系统的调制器
公开(公告)号：US20070191888A1
公开(公告)日：2007-08-16
申请号：US11352331
申请日：2006-02-13
申请人： Chua-Chin Wang , Tzung-Je Lee
发明人： Chua-Chin Wang , Tzung-Je Lee
IPC分类号： A61N1/18
CPC分类号： A61N1/32 , A61N1/36071 , A61N1/3787
摘要： The invention relates to an implantable biomedical chip with modulator for a wireless neural stimulating system. The implantable biomedical chip comprises a power regulator, a demodulator, a baseband circuit, a D/A converter, an instrumentation amplifier, an A/D converter and a modulator. According to the invention, the modulator is mounted on the implantable biomedical chip, and can achieve full-duplex communication to improve the controllability and observability. Besides, the power consumption and area occupation is reduced as compared with using discrete components. Therefore, the integration of the implantable biomedical chip can be easily accomplished.
摘要翻译：本发明涉及一种具有用于无线神经刺激系统的调制器的可植入生物医学芯片。可植入生物医学芯片包括功率调节器，解调器，基带电路，D / A转换器，仪表放大器，A / D转换器和调制器。根据本发明，调制器安装在可植入的生物医学芯片上，并且可以实现全双工通信以提高可控性和可观察性。此外，与使用分立元件相比，功耗和占地面积减少。因此，可以容易地实现植入式生物医学芯片的集成。

9. 发明授权

US08219190B2 Implantable biomedical chip with modulator for a wireless neural stimulation system 失效
标题翻译：植入式生物医学芯片与无线神经刺激系统的调制器
公开(公告)号：US08219190B2
公开(公告)日：2012-07-10
申请号：US12581915
申请日：2009-10-20
申请人： Chua-Chin Wang , Tzung-Je Lee
发明人： Chua-Chin Wang , Tzung-Je Lee
IPC分类号： A61N1/00
CPC分类号： A61N1/32 , A61N1/36071 , A61N1/3787
摘要： The invention relates to an implantable biomedical chip with modulator for a wireless neural stimulating system. The implantable biomedical chip comprises a power regulator, a demodulator, a baseband circuit, a D/A converter, an instrumentation amplifier, an A/D converter and a modulator. According to the invention, the modulator is mounted on the implantable biomedical chip, and can achieve full-duplex communication to improve the controllability and observability. Besides, the power consumption and area occupation is reduced as compared with using discrete components. Therefore, the integration of the implantable biomedical chip can be easily accomplished.
摘要翻译：本发明涉及一种具有用于无线神经刺激系统的调制器的可植入生物医学芯片。可植入生物医学芯片包括功率调节器，解调器，基带电路，D / A转换器，仪表放大器，A / D转换器和调制器。根据本发明，调制器安装在可植入的生物医学芯片上，并且可以实现全双工通信以提高可控性和可观察性。此外，与使用分立元件相比，功耗和占地面积减少。因此，可以容易地实现植入式生物医学芯片的集成。

10. 发明申请

US20110241752A1 Mixed-voltage I/O buffer 有权
标题翻译：混合电压I / O缓冲器
公开(公告)号：US20110241752A1
公开(公告)日：2011-10-06
申请号：US13067598
申请日：2011-06-13
申请人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang
发明人： Chua-Chin Wang , Wei-Chih Chang , Tzung-Je Lee , Kuo-Chan Huang
IPC分类号： H03K5/08
CPC分类号： H03K19/0013 , H03K3/356113 , H03K19/018521
摘要： A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level.
摘要翻译：混合电压I / O缓冲器包括输入缓冲电路。输入缓冲电路包括第一反相器，第一电压电平限制电路，第一电压电平上拉电路，输入级电路和逻辑校准电路。第一反相器反相输入信号以产生第一控制信号。第一电压电平限制电路限制外部信号的电压电平，以产生传输到第一逆变器的输入信号，以防止第一逆变器的电过载。第一电压上拉电路由第一控制信号控制，以提高输入到第一反相器的输入信号的电压电平。输入级电路接收第一控制信号以产生输入到核心电路的相应的数字信号。当由于输入信号具有低电压电平而使第一反相器误操作时，逻辑校准电路校准第一控制信号的电压电平。

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