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1. 发明授权

US06548856B1 Vertical stacked gate flash memory device 有权
标题翻译：垂直堆叠式门闪存器件
公开(公告)号：US06548856B1
公开(公告)日：2003-04-15
申请号：US09583403
申请日：2000-05-31
申请人： Chrong-Jung Lin , Shui-Hung Chen , Mong-Song Liang
发明人： Chrong-Jung Lin , Shui-Hung Chen , Mong-Song Liang
IPC分类号： H01L29788
CPC分类号： H01L27/11556
摘要： A method of forming a vertical transistor memory device comprises the following process steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thin floating gate layer of doped polysilicon over the tunnel oxide layer extending above the trenches. Etch the floating gate layer leaving upright floating gate strips of the floating gate layer along the sidewalls of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thin control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.
摘要翻译：形成垂直晶体管存储器件的方法包括以下处理步骤。在形成沟槽之前，在行之间形成FOX区域。然后在半导体衬底中形成具有侧壁和底部的一组沟槽，其中侧壁具有阈值注入区域。在衬底的表面附近形成掺杂的漏极区域，并且在沟槽底部的器件的底部中的掺杂源极区域之间具有相反掺杂的沟道区域。在包括沟槽的衬底上形成隧道氧化物层。在沟槽上延伸的隧道氧化物层上形成掺杂多晶硅的覆盖薄的浮动栅极层。蚀刻漂浮栅极层，沿着沟槽的侧壁留下浮动栅极层的直立浮栅条。在浮栅层和隧道氧化物层之上形成由ONO组成的电极间电介质层。在电极间电介质层上形成掺杂多晶硅的覆盖薄的控制栅极层。将控制栅层图案化为控制栅电极。形成与控制栅电极的侧壁相邻的间隔物。

2. 发明授权

US6093606A Method of manufacture of vertical stacked gate flash memory device 失效
标题翻译：垂直堆叠式闸门闪存装置的制造方法
公开(公告)号：US6093606A
公开(公告)日：2000-07-25
申请号：US35049
申请日：1998-03-05
申请人： Chrong-Jung Lin , Shui-Hung Chen , Mong-Song Liang
发明人： Chrong-Jung Lin , Shui-Hung Chen , Mong-Song Liang
IPC分类号： H01L21/8247 , H01L21/336 , H01L29/788
CPC分类号： H01L27/11556
摘要： A method of forming a vertical transistor memory device comprises the following process steps. Before forming the trenches, FOX regions are formed between the rows. Then form a set of trenches with sidewalls and a bottom in a semiconductor substrate with threshold implant regions the sidewalls. Form doped drain regions near the surface of the substrate and doped source regions in the base of the device below the trenches with oppositely doped channel regions therebetween. Form a tunnel oxide layer over the substrate including the trenches. Form a blanket thin floating gate layer of doped polysilicon over the tunnel oxide layer extending above the trenches. Etch the floating gate layer leaving upright floating gate strips of the floating gate layer along the sidewalls of the trenches. Form an interelectrode dielectric layer composed of ONO over the floating gate layer and over the tunnel oxide layer. Form a blanket thin control gate layer of doped polysilicon over the interelectrode dielectric layer. Pattern the control gate layer into control gate electrodes. Form spacers adjacent to the sidewalls of the control gate electrode.
摘要翻译：形成垂直晶体管存储器件的方法包括以下处理步骤。在形成沟槽之前，在行之间形成FOX区域。然后在半导体衬底中形成具有侧壁和底部的一组沟槽，其中侧壁具有阈值注入区域。在衬底的表面附近形成掺杂的漏极区域，并且在沟槽底部的器件的底部中的掺杂源极区域之间具有相反掺杂的沟道区域。在包括沟槽的衬底上形成隧道氧化物层。在沟槽上延伸的隧道氧化物层上形成掺杂多晶硅的覆盖薄的浮动栅极层。蚀刻漂浮栅极层，沿着沟槽的侧壁留下浮动栅极层的直立浮栅条。在浮栅层和隧道氧化物层之上形成由ONO组成的电极间电介质层。在电极间电介质层上形成掺杂多晶硅的覆盖薄的控制栅极层。将控制栅层图案化为控制栅电极。形成与控制栅电极的侧壁相邻的间隔物。

3. 发明授权

US5861634A Charge collector structure for detecting radiation induced charge during integrated circuit processing 失效
标题翻译：用于在集成电路处理期间检测辐射感应电荷的电荷收集器结构
公开(公告)号：US5861634A
公开(公告)日：1999-01-19
申请号：US871504
申请日：1997-06-09
申请人： Ching-Hsiang Hsu , Chrong-Jung Lin , Mong-Song Liang
发明人： Ching-Hsiang Hsu , Chrong-Jung Lin , Mong-Song Liang
IPC分类号： H01L23/544 , H01L23/58
CPC分类号： H01L22/34
摘要： A method and structure for the evaluation of the density of charge induced to a semiconductor substrate during exposure to radiation as a result of integrated circuits processing procedures such as ion implantation and plasma etching is disclosed. A plurality of stacked gate field effect transistors, wherein each stacked has a charge collection capacitor attached to the gate, is fabricated on a semiconductor substrate. Each charge collection capacitor has an area that is different from every other charge collection capacitor. The to substrate is exposed to a radiation source. The threshold voltage for each of the stacked gate field effect transistors is measured. The difference in threshold voltage for the stacked gate transistors is proportional to the amount of charge induced during the exposure to the radiation and the density of the charge induced by the exposure to the radiation can be calculated from the comparison of the threshold voltage and the area of the charge collection capacitors.
摘要翻译：公开了用于评价由于诸如离子注入和等离子体蚀刻的集成电路处理过程而在暴露于辐射期间对半导体衬底感生的电荷密度的评估方法和结构。在半导体衬底上制造多个堆叠栅极场效应晶体管，其中每个层叠有一个附着到栅极的电荷收集电容器。每个电荷收集电容器具有与每个其他电荷收集电容器不同的面积。将衬底暴露于辐射源。测量每个堆叠栅极场效应晶体管的阈值电压。堆叠栅极晶体管的阈值电压的差异与在曝光到辐射期间感应的电荷量成比例，并且可以从阈值电压和面积的比较来计算由暴露于辐射引起的电荷的密度的电荷收集电容器。

4. 发明授权

US08785272B2 Process to make high-K transistor dielectrics 有权
标题翻译：制造高K晶体管电介质的工艺
公开(公告)号：US08785272B2
公开(公告)日：2014-07-22
申请号：US13224059
申请日：2011-09-01
申请人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/00 , H01L21/28 , H01L21/314
CPC分类号： H01L21/0228 , C23C16/56 , H01L21/02145 , H01L21/02153 , H01L21/02159 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/4966 , H01L29/517
摘要： A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
摘要翻译：一种减少高k电介质层中的杂质的方法，包括以下步骤。提供基板。在衬底上形成具有杂质的高k电介质层。高k电介质层由MOCVD或ALCVD工艺形成。退火高k电介质层以减少高k电介质层内的杂质。

5. 发明授权

US08552522B2 Dishing-free gap-filling with multiple CMPs 有权
公开(公告)号：US08552522B2
公开(公告)日：2013-10-08
申请号：US13151666
申请日：2011-06-02
申请人： Ming-Yuan Wu , Kong-Beng Thei , Chiung-Han Yeh , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Kong-Beng Thei , Chiung-Han Yeh , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/70
CPC分类号： H01L21/76883 , H01L21/76229
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

6. 发明授权

US08461629B2 Semiconductor device and method of fabricating same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08461629B2
公开(公告)日：2013-06-11
申请号：US13178755
申请日：2011-07-08
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/66
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译：具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。可以在与芯井相邻的隔离结构上形成电阻器。在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。在一些实施例中，产生p型I / O阱和n型I / O阱。在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

7. 发明授权

US08125051B2 Device layout for gate last process 有权
标题翻译：门最后进程的设备布局
公开(公告)号：US08125051B2
公开(公告)日：2012-02-28
申请号：US12471091
申请日：2009-05-22
申请人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu , Tzung-Chi Lee
发明人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu , Tzung-Chi Lee
IPC分类号： H01L27/06 , H01L21/70 , H01L21/338 , H01L21/302
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/0629 , H01L27/0635
摘要： A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，形成在第二区域中的隔离结构，形成在隔离结构中的至少一个接合器件第二区域，以及形成在第二区域中的隔离结构上方的停止结构。

8. 发明申请

US20120025329A1 Spacer Shape Engineering for Void-Free Gap-Filling Process 有权
标题翻译：无间隙填充过程的间隔形状工程
公开(公告)号：US20120025329A1
公开(公告)日：2012-02-02
申请号：US13270585
申请日：2011-10-11
申请人： Ming-Yuah Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuah Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/78
CPC分类号： H01L21/823481 , H01L21/823468 , H01L21/823475 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在半导体衬底上形成栅叠层; 形成邻近所述栅叠层的侧壁的栅极间隔; 减薄栅间隔; 以及在所述栅极间隔物变薄的步骤之后，在所述栅极间隔物的侧壁上形成次级栅极间隔物。

9. 发明授权

US07998830B2 Semiconductor device with both I/O and core components and method of fabricating same 有权
标题翻译：具有I / O和核心部件的半导体器件及其制造方法
公开(公告)号：US07998830B2
公开(公告)日：2011-08-16
申请号：US12961167
申请日：2010-12-06
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/76
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译：具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。可以在与芯井相邻的隔离结构上形成电阻器。在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。在一些实施例中，产生p型I / O阱和n型I / O阱。在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

10. 发明授权

US07772701B2 Integrated circuit having improved interconnect structure 有权
标题翻译：具有改进的互连结构的集成电路
公开(公告)号：US07772701B2
公开(公告)日：2010-08-10
申请号：US11422769
申请日：2006-06-07
申请人： Chih-Hsiang Yao , Tai-Chun Huang , Mong-Song Liang
发明人： Chih-Hsiang Yao , Tai-Chun Huang , Mong-Song Liang
IPC分类号： H01L23/48 , H01L29/40
CPC分类号： H01L23/522 , H01L23/481 , H01L23/53228 , H01L23/5329 , H01L23/53295 , H01L2224/0401 , H01L2224/0557 , H01L2224/13023 , H01L2224/131 , H01L2924/0002 , H01L2924/13091 , H01L2924/00014 , H01L2224/05552 , H01L2924/00
摘要： An improved integrated circuit structure and method of making the same is provided. The integrated circuit structure comprises a substrate, the substrate having a top surface and a bottom surface. The top surface has a circuit device formed thereon. The structure includes a plurality of metallization layers, a bonding structure formed over the bottom surface and a conductive interconnect structure formed through said substrate.
摘要翻译：提供了一种改进的集成电路结构及其制造方法。集成电路结构包括基板，该基板具有顶表面和底表面。顶表面上形成有电路装置。该结构包括多个金属化层，形成在底表面上的接合结构和通过所述衬底形成的导电互连结构。

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